Design and Analysis of Distributed Arithmetic based FIR Filter

Akhter, Shamim; Kumar, Satyendra; Bareja, Divya

doi:10.1109/icacccn.2018.8748322

Cited by 12 publications

(10 citation statements)

References 4 publications

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“…In contrast to traditional DA, the design of [2] can work even when the input range is extended. In [6] DA and off-set binary coding (OBC) are used to overcome the difficulties associated with MAC-based FIR filter design. OBC-DA based FIR filters use less hardware than DA owing to lower LUT requirements, but have a little delay due to the additional address generating overhead [6].…”

Section: Related Workmentioning

confidence: 99%

“…In [6] DA and off-set binary coding (OBC) are used to overcome the difficulties associated with MAC-based FIR filter design. OBC-DA based FIR filters use less hardware than DA owing to lower LUT requirements, but have a little delay due to the additional address generating overhead [6]. The DA unit in [12] does not use a lookup table (LUT).…”

Section: Related Workmentioning

confidence: 99%

“…In comparison to the previous DA-based approach, it uses half the number of registers to hold the total of distinct combinations of input samples. The drawback of DA-based design is limitations imposed on the filter order, linear-phase characteristics, and accuracy while translating the multiplier operation with DA schemes of [2,6,12].…”

Section: Related Workmentioning

confidence: 99%

“…To summarize, the FIR filter and typical architectures referred to in the study are based on parallel MIMO-based FIR filter [1], DA-based design [2,6,11,12], Vedic-multiplier based design [3, 10, 7-9, 21-24] uses a polyphase based design which limits the parallelism to a smaller value and other schemes like ISC [1], OPC [4]. It is important to note the study relating to architectural enhancements is the major key for filter optimization.…”

Section: Related Workmentioning

confidence: 99%

“…The work of [2,6] is developed on Virtex-4 sx FPGA which is an optimized platform for highperformance DSP, the device selects the most favorable mix of resources for the respective application. Virtex 4 devices are formed on 90nm process technology delivered on 300mm wafers.…”

Section: Case Study 1: Related Study [1 2 and 6] Is Consideredmentioning

confidence: 99%

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Optimizing Parallel FIR Filter Architecture for Time-Sensitive Applications: A Design Approach for High-Throughput and Area Efficiency

2023

IJIES

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The advancement in very large scale integration (VLSI) technology and field programmable gate array's (FPGA) parallel constructive nature for digital circuits has made the implementation of finite impulse response (FIR) filters increasingly relevant in real-time. In FIR filters the computational complexity increases with the length of the filter; numerous techniques have been developed to design viable architectures for realizing FIR filters. The multiple input multiple output (MIMO) based parallel FIR filter architecture often requires a large area for realization as the level of parallelism and filter order increases; this study presents an architecturally enhanced, novel parallel architecture for FIR filter design which eliminates the resource dependencies on the level of parallelism. The proposed architecture addresses the issue by limiting the number of multipliers required irrespective of the change in the level of parallelism and further modifies the data flow to improve the iteration period in the proposed design. The level of parallelism (L) is fixed to 8 in the presented study as the value is neither too low nor high; it is important to note that the increase in the level of parallelism will increase the number of samples generated at a given time. The presented work is demonstrated using tap 16 FIR filter implemented on FPGA VIRTEX 4 xc4vsx35-10ff668 and VIRTEX 5 XC5VSX95T-1FF1136 platforms, and filter-order 16 FIR filter is implemented on ARTIX 7 xc7a200t-2fbg676. The functionality is verified using Xilinx ISE 14.7 and Matlab 2018 environments. The post-synthesis results and comparative study show the design validation; the proposed architecture outperforms the benchmark and conventional MIMO-based parallel FIR filter architectures with an improvement in total delay by 70% w.r.t. [2] and 93% w.r.t. [3] and 2% w.r.t. [4] as compared in case studies 1 -3. The reduction in area metric is observed as dipping in the slice requirement by 31%, 47%, and 110% and dipping in the LUT requirement by 58%, 66%, and 65%, further, the delay metric is improved by 49%, 80%, and 67% when compared with MIMO-based parallel architecture of [1] on the same platforms suggested in [2][3][4] respectively.

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Section: Related Workmentioning

confidence: 99%