Design and Analysis of an Ultrahigh-Speed Glitch-Free Fully Differential Charge Pump With Minimum Output Current Variation and Accurate Matching

Cheng, Shanfeng; Tang, Haitao; Silva-Martí­nez, J.; Karsilayan, A.I.

doi:10.1109/tcsii.2006.879100

Cited by 74 publications

(42 citation statements)

References 10 publications

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“…Literature has widely studied the charge pump for a long period. There are lots of researches on the improvement of the CP performance [2,3,4,5,6]. Researchers adopt a mismatch compensation loop, so as to mitigate the problem of the CP current mismatch for a wide range in Ref [3].…”

Section: Introductionmentioning

confidence: 99%

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A −86.88 dBc/Hz @1 MHz <i>K</i>-band fractional-N frequency synthesizer in 90-nm CMOS technology

Zhengchen

Wang

2018

IEICE Electron. Express

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Through 90-nm CMOS technology, a K-band fractional-N frequency synthesizer has been designed. This paper proposes a new analysis to evaluate the noise current of the charge pump in fractional-N frequency synthesizer. It also designs an improved charge pump (CP). In addition, it also presents the multi-modulus divider (MMD) by the retime technique. The measured phase noise achieves −93.5 dBc/Hz and −86.88 dBc/Hz for integer-N and fractional-N modes at 1 MHz offset, respectively. The in-band phase noise performance can be improved about 20 dB by the retime technique. −54.63 dBc and −50.7 dBc reference spurs are respectively revealed by the spectrum for integer-N and fractional-N modes.

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Section: Introductionmentioning

confidence: 99%

“…In addition, power ripple and environment noise can be suppressed by the charge pump with full-differential structure. Therefore, the differential charge pump compared to the single-end structure is preferred [5,6]. However, the common-mode feedback (CMFB) circuit is needed by the fully-differential structure.…”

Section: Introductionmentioning

confidence: 99%

A −86.88 dBc/Hz @1 MHz <i>K</i>-band fractional-N frequency synthesizer in 90-nm CMOS technology

Zhengchen

Wang

2018

IEICE Electron. Express

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“…Different types of FDCP are discussed in literature [1]- [5].Replica charge pump is being adopted in literature [1] and Charge sharing is supressed in charge pump by current steering technique. Switch near to output voltage can't efficiently remove charge sharing even though voltage buffer is used.…”

Section: Introductionmentioning

confidence: 99%

“…Differential cross coupled current steering is employed in literature [4] which ensures high working speed with less current mismatch. Separate techniques for mismatch suppression and variation suppression are implemented in literature [5] to have same current for output voltage variations.…”

Section: Introductionmentioning

confidence: 99%

Minimum Mismatch of Current in Fully Differential Charge Pump for Integer N- DPLL

Rajeshwari¹,

Rao²

2017

IJERA

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Fully Differential ended charge pump (FDCP) are proven to have advantages over single ended charge pump at the cost of complexity and required more power for implementation for digital phase locked loop(DPLL). Wide swing cascodebias voltage with the rail to rail operational amplifier(opamp) as common mode feedback(CMFB) provides efficient solutions for current mismatch due to its non-idealities. The FDCP is simulated across process corners using 65nm technology with tsmc foundry for10Ghz DPLL. The power consumption of FDCP is 23mW with 100uA as Charge Pump (CP) current.

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“…Moreover the noise of the charge pump is the dominant close-in phase noise contributor in a PLL [15]. Several charge pump implementations have been proposed in the associated literature [16][17][18]. In [16,17] an opamp has been used in order to keep the dc mismatch current, and hence the resultant phase offset at a minimum level and improve the overall performance.…”

Section: Introductionmentioning

confidence: 99%

Analysis and Design of Charge Pumps for Telecommunication Applications

Kalenteridis

Papathanasiou

Siskos

2010

IFIP Advances in Information and Communication Technology

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Abstract. This chapter addresses modern telecommunication integrated circuits from the synthesizer focal point; in particular it concentrates at the analysis and the design of integrated charge pump circuit blocks. It presents an overview of charge pump topologies in addition to a coherent analysis of the associated benefits and shortcomings of all circuit alternatives. Moreover a novel favorable charge pump combining current steering techniques with well utilized unity gain buffers in a novel, noiseless feedback scheme, is introduced to improve on switching speed, inherent charge pump ac noise, dead-zone interval, therefore overall steady state aliased loop noise; while on the other hand this charge pump exhibits superb DC matching characteristics in a wide output voltage range. Furthermore a well documented estimation of the active devices that contributes mostly to the overall charge pump noise performance is presented. Also an associated mathematical analysis concerning the frequency content of the charge pump noise current is given. This proposed topology manifests its applicability to charge pump alternatives, as it is demonstrated by the associated simulation results from a 0.18μm design. Because of the low-noise and accurate properties of this improved charge pump, it is ideally suited to modern telecommunication standards synthesizer realizations.

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Design and Analysis of an Ultrahigh-Speed Glitch-Free Fully Differential Charge Pump With Minimum Output Current Variation and Accurate Matching

Cited by 74 publications

References 10 publications

A −86.88 dBc/Hz @1 MHz <i>K</i>-band fractional-N frequency synthesizer in 90-nm CMOS technology

A −86.88 dBc/Hz @1 MHz <i>K</i>-band fractional-N frequency synthesizer in 90-nm CMOS technology

Minimum Mismatch of Current in Fully Differential Charge Pump for Integer N- DPLL

Analysis and Design of Charge Pumps for Telecommunication Applications

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