Design and analysis of a TB/sec memory system

Beyene, W.T.; Madden, Chris; Kim, Nam Hoon; Lee, Hae-Chang; Perego, R.; Secker, D.; Yuan, Chuck; Vaidyanath, Arun; Chang, Ken

doi:10.1109/epep.2008.4675866

Cited by 7 publications

(5 citation statements)

References 3 publications

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“…Considering the FO4 delay of a future 16nm process projected by a PTM model [Zhao and Cao 2006] and a 4 FO4 design rule [Yang 1998], we expect that the off-chip I/O bandwidth will continue to increase over the next 5 to 10 years. In addition, the recent advances in nanophotonic interconnects are expected to not only provide an increasing bandwidth, but also improve the efficiency of signaling so that the impact of I/O signaling on the overall power consumption will be reduced [Miller 2009;Beyene et al 2008]. In this article, we assume that the bandwidth and energy efficiency of off-chip channels continue to improve and focus on devising scalable router microarchitecture designs.…”

Section: Technology Trendsmentioning

confidence: 98%

“…The Cray YARC router published in 2006 has an aggregate off-chip bandwidth of 2.4Tb/s, Rambus demonstrated a 8Tb/s memory system in 2008 [Beyene et al 2008], and a hub chip in the PERCS interconnect published in 2010 has a 56×56 crossbar with 9Tb/s of raw off-chip bandwidth [Arimilli et al 2010]. The radix-64 switch fabric reported in 2012 by Satpathy et al [2012] focused on improving energy efficiency as it achieved 4.5Tb/s throughput while consuming 1.3W.…”

Section: Technology Trendsmentioning

confidence: 99%

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Scalable high-radix router microarchitecture using a network switch organization

Ahn

Son

Kim

2013

ACM Trans. Archit. Code Optim.

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As the system size of supercomputers and datacenters increases, cost-efficient networks become critical in achieving good scalability on those systems. High-radix routers reduce network cost by lowering the network diameter while providing a high bisection bandwidth and path diversity. The building blocks of these large-scale networks are the routers or the switches and they need to scale accordingly to the increasing port count and increasing pin bandwidth. However, as the port count increases, the high-radix router microarchitecture itself needs to scale efficiently. Hierarchical crossbar switch organization has been proposed where a single large crossbar used for a router switch is partitioned into many small crossbars and overcomes the limitations of conventional router microarchitecture. Although the organization provides high performance, it has limited scalability due to excessive power and area overheads by the wires and intermediate buffers.In this article, we propose scalable router microarchitectures that leverage a network within the switch design of the high-radix routers themselves. These alternative designs lower the wiring complexity and buffer requirements. For example, when a folded-Clos switch is used instead of the hierarchical crossbar switch for a radix-64 router, it provides up to 73%, 58%, and 87% reduction in area, energy-delay product, and energy-delay-area product, respectively. We also explore more efficient switch designs by exploiting the traffic-pattern characteristics of the global network and its impact on the local network design within the switch for both folded-Clos and flattened butterfly networks. In particular, we propose a bilateral butterfly switch organization that has fewer crossbars and global wires compared to the topology-agnostic folded-Clos switch while achieving better low-load latency and equivalent saturation throughput.

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Section: Technology Trendsmentioning

confidence: 98%

Section: Technology Trendsmentioning

confidence: 99%

Scalable high-radix router microarchitecture using a network switch organization

Ahn

Son

Kim

2013

ACM Trans. Archit. Code Optim.

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“…In addition, the several inches of FR4 material acts as a low-pass filter that attenuates the signal, which further contributes to ISI. As shown in [8], a PCB memory channel will see approximately 15dB of attenuation at a 16Gbps data rate (8GHz Nyquist frequency). These limitations are traditionally addressed with advanced equalization techniques, but such circuits have appreciable power, complexity and product cost implications.…”

Section: Memory System Architecturementioning

confidence: 99%

Co-design and optimization of a 256-GB/s 3D IC package with a controller and stacked DRAM

Secker

Wilson

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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This paper presents a double-sided flip-chip package. The package consists of a memory controller on one side of an organic substrate, and 3D-stacked, disaggregated memory chips, integrated with TSVs, on the opposite side. Thermal isolation is one of the key motivations for this configuration. Co-design of all physical layers is required to optimize the integrated 3D package within electrical and manufacturing constraints. Double-sided flip-chip packaging also presents unique challenges in the design of the power delivery network (PDN). A pre-layout design strategy is described, which optimizes the PDN design across 11 power domains to meet stringent impedance targets.

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“…Distant cells can be accessed by existing optical fiber networks that carry the optical equivalent of a mmW band, optically encoded with 10-40 Gb/s data [1]. The main motivations for the development of mmW technology encompassing the frequency band 55-65 GHz, pending adoption of standards are: (1) high atmospheric attenuation due to water resonance absorption, which leads to short range transmission and therefore the absence of regulatory restrictions at low power; (2) complimentary metal oxide semiconductor scaling has led to high-frequency, low-power, low-voltage transistors for digital and analog applications; (3) high wireless data rate capacity per channel using low-order coding and direct conversion radio frequency (RF) transceivers. High-order coding, capable of multiple bits per symbol and use of intermediate frequency (IF) carriers in a superheterodyne RF transceiver architecture are expected to increase the data rate substantially.…”

Section: Introductionmentioning

confidence: 99%

“…Multicore processors are becoming increasingly prevalent in computing. Multicore processors require high-throughput access to high-volume main memory with shorter access time [2]. Increasing data rates between multicore processors and main memory places increasingly difficult challenges on copper bus technology.…”

Section: Introductionmentioning

confidence: 99%

Toward a 60‐GHz wireless, low‐power, high‐throughput memory access system

Guidotti

Chowdhury

Chien

et al. 2009

Micro & Optical Tech Letters

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We propose a network of bidirectional, wireless data channels, operating in the frequency band of 55–65 GHz, as an efficient means to transfer data between processors and memory nodes distributed on separate boards within the computer box. We address channel throughput, power dissipation, form factor, and crosstalk abatement. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2969–2973, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24779

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Design and analysis of a TB/sec memory system

Cited by 7 publications

References 3 publications

Scalable high-radix router microarchitecture using a network switch organization

Scalable high-radix router microarchitecture using a network switch organization

Co-design and optimization of a 256-GB/s 3D IC package with a controller and stacked DRAM

Toward a 60‐GHz wireless, low‐power, high‐throughput memory access system

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