Co-design and optimization of a 256-GB/s 3D IC package with a controller and stacked DRAM

Secker, David; Ji, Mandy; Wilson, John; Best, Scott; Li, Ming; Cline, Julia R. K.

doi:10.1109/ectc.2012.6248934

Cited by 8 publications

(2 citation statements)

References 8 publications

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“…Other approaches have analyzed stand-alone silicon and glass interposers for system integrity [7][8], and PDN impedance reduction through optimal decoupling placement on glass interposers [9]. A double-sided configuration with memory stack on the bottom of an organic interposer [10] is limited by through-packagevia diameter and pitch in organic substrates. The 3D glass …”

Section: Introductionmentioning

confidence: 99%

Power delivery network analysis of 3D double-side glass interposers for high bandwidth applications

Kumar

Sitaraman

Cho

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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Logic-to-memory interconnections by double-side mounting on ultra-thin 3D glass interposers with Through-Package-Vias (TPVs) achieves high bandwidth (BW) (>25.6GB per second), without the complex TSV processes in logic ICs, required for wide I/O 3D-IC stack. While this interposer/packaging technology offers several advantages including power delivery by enabling thick power-ground (P/G) planes, the power distribution network (PDN) challenges such as resonances must be addressed. This paper investigates the impedance characteristics of PDN in 3D glass interposers at chip, interposer, package, and board-levels. The resonance characteristics of power and ground planes in ultrathin glass packages are compared with other interposer technologies through 3D EM simulations with variations in core thickness. Test vehicles fabricated with 10x10mm power-ground plane pairs on ultra-thin 30µm glass samples were characterized for primary resonance modes, with good model-to-hardware correlation. Self-impedance (Z11) was studied with variations in (a) number of power and ground BGA interconnections, (b) power and ground path distance, and (c) placement of decoupling capacitors. In all these three cases, the contribution of increased package-level loop inductance to total system level impedance (on-chip + interposer/package + PWB PDN) was shown to be minimal. Thus, through a combination of integrated power and ground planes, decoupling capacitors, and optimal power-ground BGA interconnection placements, ultra-thin 3D glass interposers can achieve the target impedance guidelines for high BW systems.

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Section: Introductionmentioning

confidence: 99%

Power delivery network analysis of 3D double-side glass interposers for high bandwidth applications

Kumar

Sitaraman

Cho

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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“…Redistribution Layer metal layers on both sides of the interposer along with TSVs passing through it provide connections between the two sides. In [39], one such solution is proposed with a logic controller stacked on top of a substrate. While the whole DRAM stack along with its controller are placed on the bottom of the substrate.…”

mentioning

confidence: 99%

A Modular Shared L2 Memory Design for 3-D Integration

Azarkhish

Rossi

Loi

et al. 2015

IEEE Trans. VLSI Syst.

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Large required size, and tolerance to latency and variations in memory access time make L2 memory a suitable option for 3-D integration. In this paper, we present a synthesizable 3-D-stackable L2 memory IP component, which can be attached to a cluster-based multicore platform through its network-on-chip interfaces offering high-bandwidth memory access with low average latency. Our design implements a scalable 3-D-nonuniform memory access (NUMA) architecture based on low latency logarithmic interconnects, which allows stacking of multiple identical memory dies (MDs), supports multiple outstanding transactions, and achieves high clock frequencies due to its highly pipelined nature. We implemented our design with STMicroelectronics CMOS-28-nm low-power technology and obtained a clock frequency of 500 MHz (limited by the access time of the memory arrays, whereas its logic components can operate up to 1 GHz), up to eight stacked dies (4 MB) with a memory density loss of 9%. Benchmark simulation results demonstrate that the addition of 3-D-NUMA to a multicluster system can lead to an average performance boost of 34%. Furthermore, experiments and estimations confirm that 3-D-NUMA is energy and power efficient (38% power reduction due to an architectural clock gating scheme), temperature friendly (over 40°C temperature reduction), and has unique features suitable for low-cost manufacturing (2.3× cost reduction due to identical MD layouts). Finally, 22% yield improvement is achievable in 3-D-NUMA compared with its 2-D counterparts, using the state of the art through-silicon-via technologies.Index Terms-3-D integration, nonuniform memory access (NUMA), physical implementation, tightly coupled data memory.

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3D Stacking of RAM–Processor Chips Using TSV

2014

Vertical 3D Memory Technologies

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Co-design and optimization of a 256-GB/s 3D IC package with a controller and stacked DRAM

Cited by 8 publications

References 8 publications

Power delivery network analysis of 3D double-side glass interposers for high bandwidth applications

Power delivery network analysis of 3D double-side glass interposers for high bandwidth applications

A Modular Shared L2 Memory Design for 3-D Integration

3D Stacking of RAM–Processor Chips Using TSV

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