Design & Implementation of Approximate 7:2 Compressor Based 16-bit Dadda Multiplier using Verilog

Abstract

Now a days the technology is growing day by day with faster rate. Particularly the usage of electronics is increasing in wide range of ways depending on their intended purpose and preferences. In this regard multipliers are playing a vital role because they allow us to perform complex arithmetic operations involving large numbers more efficiently. Instead of performing a series of addition or subtraction operations, a multiplier allows us to perform the operation in a single step within no time that is the challenge of today’s world. So in addition to being more efficient, multipliers also have practical applications in fields such as engineering, computer science, and cryptography also used , for example, in the design of digital circuits and in the encryption and decryption of data. Overall, multipliers playing an important role in mathematics and its applications and are essential tools for performing complex computations efficiently. Compressors play a vital role in realizing the high speed multipliers. In error resilient applications such as Image processing, Multimedia and Matrix multiplication the approximate computing is used, which provides meaningful results faster with lower power consumption. In previous work the compressors are designed using the full adders which provides accurate results. The 4:2 and 5:2 approximate compressors are then introduced with 18% delay reduction and ADP reduction up to 52%. Now the further work concentrated on the implementation of 7:2 Approximate Compressor based multiplier, to further enhance the performance of multipliers. The proposed design will be expected to provide maximum extent of reduction in area, delay or power consumption and achieves improvement in terms of speed as compared to the 4:2 and 5:2 compressor based approximate multiplier.