IECON'03. 29th Annual Conference of the IEEE Industrial Electronics Society (IEEE Cat. No.03CH37468)
DOI: 10.1109/iecon.2003.1280328
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Design a modulator and demodulator SSB by using DSP processor TMS320C50 for PLC systems

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Cited by 2 publications
(1 citation statement)
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“…It has a set of procedure bus, three sets of data bus, highly parallel arithmetic logic unit AL , dedicated hardware logic on-chip memor , high CPU frequency up to 100MHZ, and enhanced HPI port, therefore one write operation and two read ones can be completed in one cycle. Moreover, a variety of digital signal processing algorithms can be quickly achieved as a result of specialized hardware multiplier, extensive use of pipelining operation and special DSP instructions [5]. The conversion chips AD7822 and DAC08 are selected in this paper to achieve high-speed and synchronous digital-toanalog conversion.…”
Section: B Hardware Designmentioning
confidence: 99%
“…It has a set of procedure bus, three sets of data bus, highly parallel arithmetic logic unit AL , dedicated hardware logic on-chip memor , high CPU frequency up to 100MHZ, and enhanced HPI port, therefore one write operation and two read ones can be completed in one cycle. Moreover, a variety of digital signal processing algorithms can be quickly achieved as a result of specialized hardware multiplier, extensive use of pipelining operation and special DSP instructions [5]. The conversion chips AD7822 and DAC08 are selected in this paper to achieve high-speed and synchronous digital-toanalog conversion.…”
Section: B Hardware Designmentioning
confidence: 99%