Description of limit cycles in sigma-delta modulators

Abstract

Abstract-A mathematical framework, based on state-space modeling, for the description of limit cycles (LCs) of 1-bit sigma-delta modulators (SDMs) is presented. It is proved that periodicity in bit output pattern of the SDM implies a periodic orbit in state-space variables. While the state-space description is generally applicable for periodic inputs, the focus is on dc inputs, since this represents the most relevant practical condition. An outcome of the analysis is that, in general, for an th-order SDM, at least 1 initial conditions need to be fixed in order to have LC behavior. Expressions for the minimum disturbance of the input or initial conditions that is needed to break up a LC are also presented. Special focus is given to the case where the disturbance takes the form of "dithering the quantizer", and it is shown that this form of dither is a suboptimal approach to remove LCs. The stability of LCs is determined, and it is demonstrated that a resonator section, as often employed to increase the dynamic range of an SDM, has an adverse effect on LC behavior in that it stabilizes LCs. Furthermore, the experimental observation that high order SDMs are less susceptible to LCs is underpinned. Finally, some examples are provided which illustrate the theoretical results.

Nonlinear Stability Prediction of Multibit Delta–Sigma Modulators for Sinusoidal Inputs

“…One technique is to model the quantizer as a threshold function in the state equations, which gets complicated for higher-order Δ-Σ modulators and is limited to 1 st -and 2 nd -order Δ-Σ modulators [1]. Another approach to simplify the analysis has been to assume a DC input to the Δ-Σ modulator [2]- [7]. In [8], separate signal and quantization noise nonlinear gains have been used for the stability analysis of 2 nd -and 3 rd -order Δ-Σ modulators for DC and sinusoidal inputs using the root locus approach.…”

“…It can be observed that all Jaswinder Lota, Senior Member, IEEE, M. Al-Janabi, Member, IEEE and Izzet Kale, Member, IEEE Nonlinear stability prediction of multi-bit deltasigma modulators for sinusoidal inputs the reported approaches, to the authors' best knowledge, relate to the stability of one-bit ∆-Σ modulators. Furthermore, some of these approaches assume DC inputs and/or are restricted to lower-order ∆-Σ modulators [1]- [7], [10].…”

Comparative study of the MASH digital delta-sigma modulators

“…The architectures of EFMs decide the sequence length of DDSMs. Since a short sequence length results in unwanted frequency components in the output frequency spectrum [1], much research has been done into maximising the sequence length. There are two approaches to lengthen the sequence length: stochastic and deterministic methods.…”

A method for searching the limit cycles of high order sigma-delta modulators

“…This enables to carry out an exhaustive search for cyclic sequences up to a length of 40 clock periods. In [8], [9] authors use state space approach and present a mathematical framework for the description of limit cycles in 1-bit Σ∆ modulators for constant inputs.…”