Dependence of DC Parameters on Layout and Low-Frequency Noise Behavior in Strained-Si nMOSFETs Fabricated by Stress-Memorization Technique

High-performance sidewall damascened tri-gate poly-si TFTs with the strain proximity free technique and stress memorization technique

“…The transfer characteristics of the SC-SWDTG TFTs with a top silicon nitride liner of 100 nm, with/without the RTA treatment are shown in figure 3. To further include and enhance the strain effect into the poly-Si channels [15,16,[19][20][21], improve the crystallinity of the poly-Si channels [26], and decrease the total trap density (N T ) in the poly-Si channels [26,27], a high-temperature and transient treatment was implemented by the RTA process at 1050 °C for 1 s. Nevertheless, the mean grain size is only mildly affected by the RTA treatment because the variation of the mean grain size is slight before and after an additional RTA treatment [28]. Thus, the SC-SWDTG TFT-B shows a higher drain current than that of the SC-SWDTG TFT-A.…”

“…The SC-SWDTG TFTs were fabricated with different tensile stress by adjusting the top silicon nitride thickness (100 nm and 200 nm) in the N/O/N sandwiched structure. Although the poly-Si channels were not clamped by the top and bottom silicon nitride liners, the strain of the top and bottom silicon nitride liners have been directly added and memorized into the poly-Si channels by the SPFT and the SMT [15,16,[19][20][21]. The thicker (200 nm) and thinner (100 nm) top silicon nitride liners are annealed by RTA treatment for a different thickness comparison, as shown in figure 3.…”

“…Recently, many process-induced strain techniques such as a contact etching stop layer (CESL) [17], an embedded source/drain (S/D) [17], a strain proximity technique (SPT) [18], a strain proximity free technique (SPFT) [15,16], a dual stress liners (DSL) [18], and a poly amorphorization implant (PAI) with stress memorization technique (SMT) [19][20][21], have been proposed and used to enhance device performance. Nevertheless, the increment of carrier mobility in the devices would obviously degrade as the gate pitches are aggressively scaled down to 100 nm or beyond [17,[22][23][24].…”