Dependence-conscious global register allocation

Ambrosch, Wolfgang; Ertl, M. Anton; Beer, Felix; Krall, Andreas

doi:10.1007/3-540-57840-4_28

Cited by 12 publications

(5 citation statements)

References 14 publications

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“…The literature contains a lot of techniques for minimizing the register requirement in superscalar (sequential) codes that are sensitive to ILP scheduling (2,18,20,23,25,26) . Others prefer to combine ILP scheduling with register allocation.…”

Section: Related Work and Discussionmentioning

confidence: 99%

“…The extended DDG is presented in Part (3). The VLIW schedule in Part (2) shows that it requires two registers while its total schedule time is equal to 8. As can be seen, the extended DDG constructed from this schedule has a null cycle between c and d. We can easily see that we cannot construct any extended DDG without a cycle, since the minimal register need of the DAG is 2: the lifetimes intervals of the values c and d must be necessary serialized after the intervals of a and b if we want to require only two registers.…”

Section: Eliminating Cycles With Non-positive Latenciesmentioning

confidence: 99%

“…2 Then, our notations become V R for the set of values of the implicit type we consider, E R for the set of flow edges through a register of that type, δ r and δ w for reading/writing delays, and RN σ (G) for the register need of the type we consider. Also, we use the notation u for both the operation u and the value of the considered type it produces.…”

Section: An Algorithmic Heuristics For Reducing the Register Saturationmentioning

confidence: 99%

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Register Saturation in Instruction Level Parallelism

Touati¹

2005

Int J Parallel Prog

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International audienceThe registers constraints are usually taken into account during the scheduling pass of an acyclic data dependence graph (DAG): any schedule of the instructions inside a basic block must bound the register requirement under a certain limit. In this work, we show how to handle the register pressure before the instruction scheduling of a DAG. We mathematically study an approach which consists in managing the exact upper-bound of the register need for all the valid schedules of a considered DAG, independently of the functional unit constraints. We call this computed limit the register saturation (RS) of the DAG. Its aim is to detect possible obsolete register constraints, i.e., when RS does not exceed the number of available registers. If it does, we add some serial edges to the original DAG such that the worst register need does not exceed the number of available registers. We propose an appropriate mathematical formalism for this problem. Our generic processor model takes into account superscalar, VLIW and EPIC/IA64 architectures. Our deeper analysis of the problem and our formal methods enable us to provide nearly optimal heuristics and strategies for register optimization in the face of ILP

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Section: Related Work and Discussionmentioning

confidence: 99%

Section: Eliminating Cycles With Non-positive Latenciesmentioning

confidence: 99%

Section: An Algorithmic Heuristics For Reducing the Register Saturationmentioning

confidence: 99%

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Register Saturation in Instruction Level Parallelism

Touati¹

2005

Int J Parallel Prog

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“…The interaction between register allocation and code scheduling has been studied by several researchers. Suggested approaches include using post-pass scheduling (after register allocation) to avoid overusing registers and causing additional spills [16,30], construction of a register dependence graph (used by instruction scheduling) during register allocation to reduce false scheduling dependences [44,45], and other methods to combine the two phases into a single pass [4]. Earlier research has also studied the interaction between register allocation and instruction selection [3] and suggested using a common representation language for all the phases of a compiler, allowing them to be re-invoked repeatedly to take care of several such phase re-ordering issues.…”

Section: Related Workmentioning

confidence: 99%

Analyzing and addressing false interactions during compiler optimization phase ordering

Jantz

Kulkarni

2013

Softw. Pract. Exper.

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Compiler optimization phase ordering is a fundamental, pervasive, and long-standing problem for optimizing compilers. This problem is caused by interacting optimization phases producing different codes when applied in different orders. Producing the best phase ordering code is very important in performance-oriented and cost-constrained domains, such as embedded systems. In this work, we analyze the causes of the phase ordering problem in our compiler, Very Portable Optimizer (VPO), and report our observations. We devise new techniques to eliminate, what we call, false phase interactions in our compiler. We find that reducing such false phase interactions significantly prunes the phase order search space. We also develop and study algorithms to find the best average performance that can be delivered by a single phase sequence over our benchmark set and discuss the challenges in resolving this important problem. Our results show that there is no single sequence in VPO that can achieve the optimal phase ordering performance across all functions.ANALYZING FALSE INTERACTIONS DURING OPTIMIZATION PHASE ORDERING 645 set. Therefore, in this work, we also explore this problem of automatically finding the best average performance that can be achieved by any single compiler phase sequence in our compiler and discuss the challenges in addressing this issue. Our study empirically shows the non-existence of a single phase sequence that can achieve optimal code for all functions.Although phase ordering is a pervasive issue across all or most compilers, we must necessarily restrict this study to a single compiler. The presence of an exhaustive framework for phase ordering research, along with our intimate knowledge of its internal organization, made VPO the best choice for us to conduct this research. However, we believe that our motivation and methodology for exploring and addressing phase interaction issues should be more generally applicable to other compilers. Most of all, we believe that even though different compilers may have different optimization phases, implementations, and phase interactions, this study shows the potential and benefit of understanding such interactions to guide future implementation decisions that minimize the phase ordering problem and generate higher-quality code in compilers. The major contributions of this research work are as follows:ANALYZING FALSE INTERACTIONS DURING OPTIMIZATION PHASE ORDERING 647 § In theory, compiler optimizations can undo changes made by preceding phases and introduce back-edges in the directed graph. However, for our set of 244 benchmark functions, the exhaustive search algorithm only produced 'acyclic' graphs (no back-edges), and so we call them DAGs in this paper. The acyclic nature of the graphs is not a requirement for the exhaustive search algorithm. ANALYZING FALSE INTERACTIONS DURING OPTIMIZATION PHASE ORDERING 651 ** Applying conservative copy propagation explicitly as a distinct reorderable increases the size of the search space by over 77%, on average, and reduces...

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“…The interaction between register allocation and 5. r [12] code scheduling has been studied by several researchers. Suggested approaches include using postpass scheduling (after register allocation) to avoid overusing registers and causing additional spills [13,9], construction of a register dependence graph (used by instruction scheduling) during register allocation to reduce false scheduling dependences [25,3], and other methods to combine the two phases into a single pass [10]. Earlier research has also studied the interaction between register allocation and instruction selection [4], and suggested using a common representation language for all the phases of a compiler, allowing them to be re-invoked repeatedly to take care of several such phase re-ordering issues.…”

Section: Related Workmentioning

confidence: 99%

Eliminating false phase interactions to reduce optimization phase order search space

Jantz

Kulkarni

2010

Proceedings of the 2010 International Conference on Compilers, Architectures and Synthesis for Embedded Systems

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Compiler optimization phase ordering is a longstanding problem, and is of particular relevance to the performance-oriented and costconstrained domain of embedded systems applications. Optimization phases are known to interact with each other, enabling and disabling opportunities for successive phases. Therefore, varying the order of applying these phases often generates distinct output codes, with different speed, code-size and power consumption characteristics. Most current approaches to address this issue focus on developing innovative methods to selectively evaluate the vast phase order search space to produce a good (but, potentially suboptimal) representation for each program. In contrast, the goal of this work is to study and identify common causes of optimization phase interactions across all phases, and then devise techniques to eliminate them, if and when possible. We observe that several phase interactions are caused by false register dependence during many optimization phases. We further find that depending on the implementation of optimization phases, even an increased availability of registers may not be able to significantly reduce such false register dependences. We explore the potential of cleanup phases, such as register remapping and copy propagation, at reducing false dependences. We show that innovative implementation and application of these phases to reduce false register dependences not only reduces the size of the phase order search space substantially, but can also improve the quality of code generated by optimizing compilers.

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Dependence-conscious global register allocation

Cited by 12 publications

References 14 publications

Register Saturation in Instruction Level Parallelism

Register Saturation in Instruction Level Parallelism

Analyzing and addressing false interactions during compiler optimization phase ordering

Eliminating false phase interactions to reduce optimization phase order search space

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