Dependability analysis using a fault injection tool based on synthesizability of HDL models

Zarandi, Hamid R.; Miremadi, Seyed Ghassem; Ejlali, Alireza

doi:10.1109/dftvs.2003.1250147

Cited by 54 publications

(21 citation statements)

References 19 publications

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“…For the first phase and injecting the transient single bit-flip faults at the behavioral level in node 2, the SINJECT fault injection tool [21] was used. There are three steps to use of SINJECT tool: Step1: When the given workload is applied, behaviors of the error indicator registers of node 2 and node 4 in a fault-free network are simulated and stored.…”

Section: Error Types Determination Processmentioning

confidence: 99%

Categorizing and Analysis of Activated Faults in the FlexRay Communication Controller Registers

Sedaghat

Miremadi

2009

2009 14th IEEE European Test Symposium

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Section: Error Types Determination Processmentioning

confidence: 99%

Categorizing and Analysis of Activated Faults in the FlexRay Communication Controller Registers

Sedaghat

Miremadi

2009

2009 14th IEEE European Test Symposium

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“…The method we are using in this article is the Simulation based method using the SINJECT fault injection and evaluation software developed in Sharif University of Technology [2]. The fault models that are used in this article are bit-flip and single Stuck-at faults inside the processor.…”

Section: Introductionmentioning

confidence: 99%

Reducing of soft error effects on a MIPS-based dual-core processor

Didehban

Khoshbakht

Zarandi

et al. 2010

2010 15th CSI International Symposium on Computer Architecture and Digital Systems

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In this paper, a simulation-based fault injection analysis of a MIPS-based dual-core processor is presented, an approach is proposed to improve the reliability of most vulnerable parts of the processor components and then the improvement is evaluated. In the first series of experiments, a total of 9100 transient faults were injected in 114 different fault sites of the processor. These experiments demonstrate that the Message Passing Interface, the Arbiter and the Program Counters are the most vulnerable parts of the processor. Thus, these parts were selected as targets for the improvement. The fault tolerance method used for improving the Arbiter is based on using the Triple Modular Redundancy. As for the Message Passing Interface and the Program Counters the single bit error correction Hamming code is used. The experimental results show 11.8% improvement in error recovery and 15.1% reduction of failure rate at the cost of 1.01% area overhead.

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“…This experiment evaluates the reliability of NoC router against various fault models through simulation-based method with the help of SINJECT. SINJECT is a fault injection tool which examines the robustness of modeled system in Verilog or VHDL [9]. This paper is organized as follows: Section 2 introduces the implemented NoC router in this experiment.…”

Section: Introductionmentioning

confidence: 99%