Demonstration of Wafer Scale Fabrication of 3-D Stacked Transmitter and Receiver Modules for Optical Interconnects

Duan, P.; Raz, O.; Smalbrugge, Barry; Dorren, Hjs Harm

doi:10.1109/jlt.2013.2285304

Cited by 17 publications

(5 citation statements)

References 17 publications

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“…The testing results, together with performance of SFP+ own transmitter, acting as a reference, are shown in Fig.15. The deviation of the receiver sensitivity when operating the 11 VCSEL channels is 1.0 dB, with the worst performance associated with the side channels (10,11). This may be due to the small variations in the ohmic resistance after the compression bonding of the VCSELs, which may have resulted from non-uniform force at the edges.…”

Section: A Transmitter Testingmentioning

confidence: 99%

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Chip Scale 12-Channel 10 Gb/s Optical Transmitter and Receiver Subassemblies Based on Wet Etched Silicon Interposer

Guelbenzu

et al. 2017

J. Lightwave Technol.

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Section: A Transmitter Testingmentioning

confidence: 99%

“…Three dimensional (3D) stacking is an effective way to get short connection and high bandwidth density, and it can be achieved by reflow of thick photoresist on wafer scale [11]. However, the thermal coupling between CMOS and optoelectronics becomes a serious issue.…”

Section: Introductionmentioning

confidence: 99%

Chip Scale 12-Channel 10 Gb/s Optical Transmitter and Receiver Subassemblies Based on Wet Etched Silicon Interposer

Guelbenzu

et al. 2017

J. Lightwave Technol.

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“…This approach enables individual functions, for example, configurable logic, memory, and serial transceivers to be fabricated using optimized processes before final integration, as well as reducing overall costs through reduced individual die area. An alternative to the interposer approach is to attach photonic transceivers directly to the CMOS chip in a 3-D arrangement [114]. Ultimately this offers minimum interconnect delays between circuit elements and maximum bandwidth between layers but is challenging due to thermal, stress, and reliability issues and requires new methods for testing.…”

Section: A Photonic Integrationmentioning

confidence: 99%

Reconfigurable Network Systems and Software-Defined Networking

et al. 2015

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This paper reviews the current state of the art in reconfigurable network systems, covering hardware reconfiguration and its interplay with software-defined networking (SDN).ABSTRACT | Modern high-speed networks have evolved from relatively static networks to highly adaptive networks facilitating dynamic reconfiguration. This evolution has influenced all levels of network design and management, introducing increased programmability and configuration flexibility. This influence has extended from the lowest level of physical hardware interfaces to the highest level of network management by software. A key representative of this evolution is the emergence of software-defined networking (SDN). In this paper, we review the current state of the art in reconfigurable network systems, covering hardware reconfiguration, SDN, and the interplay between them. We take a top-down approach, starting with a tutorial on software-defined networks. We then continue to discuss programming languages as the linking element between different levels of software and hardware in the network. We review electronic switching systems, highlighting programmability and reconfiguration aspects, and describe the trends in reconfigurable network elements. Finally, we describe the state of the art in the integration of photonic transceiver and switching elements with electronic technologies, and consider the implications for SDN and reconfigurable network systems.

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“…In packaging solutions, 3D stacking is the best way to achieve highest bandwidth density and short connections [10]. Also the reflowing of photoresist has been demonstrated as a bridge for connecting traces at a low cost process [11]. However, when stacking dies, thermal removal becomes a big issue [12,13].…”

Section: Introductionmentioning

confidence: 99%

Wet-Etched Three-Level Silicon Interposer for 3-D Embedding and Connecting of Optoelectronic Dies and CMOS ICs

Smalbrugge

et al. 2018

IEEE Trans. Compon., Packag. Manufact. Technol.

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Demonstration of Wafer Scale Fabrication of 3-D Stacked Transmitter and Receiver Modules for Optical Interconnects

Cited by 17 publications

References 17 publications

Chip Scale 12-Channel 10 Gb/s Optical Transmitter and Receiver Subassemblies Based on Wet Etched Silicon Interposer

Chip Scale 12-Channel 10 Gb/s Optical Transmitter and Receiver Subassemblies Based on Wet Etched Silicon Interposer

Reconfigurable Network Systems and Software-Defined Networking

Wet-Etched Three-Level Silicon Interposer for 3-D Embedding and Connecting of Optoelectronic Dies and CMOS ICs

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