Demonstration of Unsupervised Learning With Spike-Timing-Dependent Plasticity Using a TFT-Type NOR Flash Memory Array

Kim, Chul-Heung; Soo-Chang, Lee; Woo, Sung Yun; Kang, Won-Mook; Lim, Suhwan; Bae, Jong-Ho; Kim, Jaeha; Lee, Jong-Ho

doi:10.1109/ted.2018.2817266

Cited by 57 publications

(41 citation statements)

References 22 publications

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“…Figure 6 shows the simulation results when applying ten program pulses to the selected cell, and it can be confirmed here that the current decreases as the threshold voltage shifts in the positive direction. For the unselected cells, the floating SLs/DLs inhibit FN tunneling by reducing the electric field at the tunneling oxide, which is a self-boost inhibit scheme ( Figure 7 ) [ 15 ]. Because 0 V is applied to the word lines of the other inhibited cells, the threshold voltage of those cells does not change.…”

Section: Resultsmentioning

confidence: 99%

“…Another synaptic device candidate is flash memory, which is quite mature and has the advantage of stable operation.in particular, NOR/AND-type flash memory has been studied in an effort to implement a synaptic array [ 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 ]. However, the cell size in this case exceeds that of memristors, and there are challenges when attempting to scale a large number of synapse arrays.…”

Section: Introductionmentioning

confidence: 99%

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3D AND-Type Stacked Array for Neuromorphic Systems

et al. 2020

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NOR/AND flash memory was studied in neuromorphic systems to perform vector-by-matrix multiplication (VMM) by summing the current. Because the size of NOR/AND cells exceeds those of other memristor synaptic devices, we proposed a 3D AND-type stacked array to reduce the cell size. Through a tilted implantation method, the conformal sources and drains of each cell could be formed, with confirmation by a technology computer aided design (TCAD) simulation. In addition, the cell-to-cell variation due to the etch slope could be eliminated by controlling the deposition thickness of the cells. The suggested array can be beneficial in simple program/inhibit schemes given its use of Fowler–Nordheim (FN) tunneling because the drain lines and source lines are parallel. Therefore, the conductance of each synaptic device can be updated at low power level.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

3D AND-Type Stacked Array for Neuromorphic Systems

et al. 2020

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“…The pattern classification was performed using a MATLAB simulator. For the simulation, the characteristics of a TFT-type NOR flash memory synaptic device in our previous work ( Kim et al, 2018 ) were adopted for its high performance in a neural network. Figure 11A shows a three-dimensional schematic view of an array of TFT-type NOR flash memory synaptic devices.…”

Section: Resultsmentioning

confidence: 99%

“…In the learning process, the synchronized binary 28 × 28 input pulses were applied to the synapse array. The behavioral modeling of synaptic devices and the proposed spike-timing-dependent plasticity (STDP) learning rule ( Kim et al, 2018 ) were used for learning the synaptic weights. The I&F, reset and lateral inhibition functions were used for systematic operation of multiple neurons.…”

Section: Methodsmentioning

confidence: 99%

A Split-Gate Positive Feedback Device With an Integrate-and-Fire Capability for a High-Density Low-Power Neuron Circuit

et al. 2018

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Hardware-based spiking neural networks (SNNs) to mimic biological neurons have been reported. However, conventional neuron circuits in SNNs have a large area and high power consumption. In this work, a split-gate floating-body positive feedback (PF) device with a charge trapping capability is proposed as a new neuron device that imitates the integrate-and-fire function. Because of the PF characteristic, the subthreshold swing (SS) of the device is less than 0.04 mV/dec. The super-steep SS of the device leads to a low energy consumption of ∼0.25 pJ/spike for a neuron circuit (PF neuron) with the PF device, which is ∼100 times smaller than that of a conventional neuron circuit. The charge storage properties of the device mimic the integrate function of biological neurons without a large membrane capacitor, reducing the PF neuron area by about 17 times compared to that of a conventional neuron. We demonstrate the successful operation of a dense multiple PF neuron system with reset and lateral inhibition using a common self-controller in a neuron layer through simulation. With the multiple PF neuron system and the synapse array, on-line unsupervised pattern learning and recognition are successfully performed to demonstrate the feasibility of our PF device in a neural network.

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“…In spite of this structure, the program operation can still be performed by CHEI at the source side; as for the erase operation, instead, a positive voltage is applied between the gate and source, resulting in the emission of stored electrons toward the gate by FN tunneling. Although, recently, some more effort was devoted to build new custom synaptic devices and test them in SNNs [49][50][51], a more convincing proof of the feasibility of the floating-gate transistor to build large-scale neuromorphic systems comes from a different approach. The basic idea consists in slightly modifying the routing of commercially available NOR Flash memory arrays to enable a single-cell selective erase operation while keeping the cell structure unchanged.…”

Section: Memory Transistors As Synaptic Devices In Artificial Neural mentioning

confidence: 99%

Memristive and CMOS Devices for Neuromorphic Computing

et al. 2020

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Neuromorphic computing has emerged as one of the most promising paradigms to overcome the limitations of von Neumann architecture of conventional digital processors. The aim of neuromorphic computing is to faithfully reproduce the computing processes in the human brain, thus paralleling its outstanding energy efficiency and compactness. Toward this goal, however, some major challenges have to be faced. Since the brain processes information by high-density neural networks with ultra-low power consumption, novel device concepts combining high scalability, low-power operation, and advanced computing functionality must be developed. This work provides an overview of the most promising device concepts in neuromorphic computing including complementary metal-oxide semiconductor (CMOS) and memristive technologies. First, the physics and operation of CMOS-based floating-gate memory devices in artificial neural networks will be addressed. Then, several memristive concepts will be reviewed and discussed for applications in deep neural network and spiking neural network architectures. Finally, the main technology challenges and perspectives of neuromorphic computing will be discussed.

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Demonstration of Unsupervised Learning With Spike-Timing-Dependent Plasticity Using a TFT-Type NOR Flash Memory Array

Cited by 57 publications

References 22 publications

3D AND-Type Stacked Array for Neuromorphic Systems

3D AND-Type Stacked Array for Neuromorphic Systems

A Split-Gate Positive Feedback Device With an Integrate-and-Fire Capability for a High-Density Low-Power Neuron Circuit

Memristive and CMOS Devices for Neuromorphic Computing

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