Demonstration of superconducting memory for an RQL CPU

Burnett, Randall; Clarke, Ryan; Lee, Timothy J.; Hearne, Harold; Vogel, Jacob; Herr, Q.P.; Herr, Anna

doi:10.1145/3240302.3270313

Cited by 5 publications

(4 citation statements)

References 1 publication

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“…Superconducting memory has been developed in RSFQ [32][33][34] , RQL 35 , AQFP 36 , with an allsuperconducting memory achieving a density of up to 1 Mb/cm 2 , 37 and magnetic-enhanced memory research providing a route to higher density without further advancements in lithography 38 . The shift regis-ter, being more relevant here, is a fast memory for on chip with processing, related to "registers" and cache.…”

Section: G Discussionmentioning

confidence: 99%

Asynchronous Reversible Computing Unveiled Using Ballistic Shift Registers

Osborn¹,

Wustmann²

2022

Preprint

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Reversible logic has recently progressed in superconducting circuits and promises momentous improvements in computing efficiency relative to irreversible logic developed by industry in semiconductor circuits. Superconducting logic uses single flux quanta (SFQ) to represent bits, and unlike their irreversible SFQ-logic relatives the bits may switch state with extremely low dissipation. Here we propose and simulate ballistic shift registers (BSRs). These devices are reversible and dramatically more energy-efficient than previous ones, including a pioneering one developed before the advent of SFQ logic. The BSR is ballistic because no power is supplied to the gate other than the input bits themselves; the results are conveyed as slightly slower output bits. The BSR uses an SFQ of either polarity for the stored bit as well as ballistic fluxons. The BSR additionally uses shunt capacitors and the nonlinearity of the ends of long Josephson junctions to support partial fluxons and energy-conserving dynamics. The BSRs are multi-port and allow asynchronous bit arrivalimportant functionalities not available in previous reversible gates. During their interaction, the stored and the moving bits swap their bit states, resulting in the shift-register operation. We show that two BSRs operate in sequence without power added. In addition, we show that a BSR circuit with two inputs allows a bit state to be conveyed on different outputs. This constitutes the first asynchronous ballistic 2-input gate. Finally, for a more intuitive understanding of the dynamics, we introduce a collective coordinate model. It describes the 1-bit BSR dynamics with the motion of two coordinates in a potential determined by the states of the input bit and the initial stored SFQ. We discuss the potential for this SFQ logic type in the context of energy efficiency, parameter margins, logical depth, and speed.

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Section: G Discussionmentioning

confidence: 99%

Asynchronous Reversible Computing Unveiled Using Ballistic Shift Registers

Osborn¹,

Wustmann²

2022

Preprint

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“…This memory, NDRO, only utilizes JJs and so is significantly less dense than the magnetic memory alternatives. However, its characteristics made it a good fit for implementing register files and other small memory arrays that support the operation of a processor (Burnett et al, 2018).…”

Section: Superconducting Digital Electronics Developmentmentioning

confidence: 99%

BrainFreeze: Expanding the Capabilities of Neuromorphic Systems Using Mixed-Signal Superconducting Electronics

Tschirhart

Segall

2021

Front. Neurosci.

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Superconducting electronics (SCE) is uniquely suited to implement neuromorphic systems. As a result, SCE has the potential to enable a new generation of neuromorphic architectures that can simultaneously provide scalability, programmability, biological fidelity, on-line learning support, efficiency and speed. Supporting all of these capabilities simultaneously has thus far proven to be difficult using existing semiconductor technologies. However, as the fields of computational neuroscience and artificial intelligence (AI) continue to advance, the need for architectures that can provide combinations of these capabilities will grow. In this paper, we will explain how superconducting electronics could be used to address this need by combining analog and digital SCE circuits to build large scale neuromorphic systems. In particular, we will show through detailed analysis that the available SCE technology is suitable for near term neuromorphic demonstrations. Furthermore, this analysis will establish that neuromorphic architectures built using SCE will have the potential to be significantly faster and more efficient than current approaches, all while supporting capabilities such as biologically suggestive neuron models and on-line learning. In the future, SCE-based neuromorphic systems could serve as experimental platforms supporting investigations that are not feasible with current approaches. Ultimately, these systems and the experiments that they support would enable the advancement of neuroscience and the development of more sophisticated AI.

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“…SFQ cells are also inherently synchronous, relying on clock signals, with memory integrated into the logic. Although creating dense memory structures in SFQ can be challenging [26][27][28][29], it is exceptionally well-suited for in-memory computation. The combination of neuromorphic architecture and SFQ technology is advantageous.…”

Section: Introductionmentioning

confidence: 99%

Hybrid synaptic structure for spiking neural network realization

Razmkhah,

Karamuftuoglu,

Bozbey

2024

Supercond. Sci. Technol.

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Neural networks and neuromorphic computing represent fundamental paradigms as alternative approaches to Von-Neumann-based implementations, advancing in the applications of deep learning and machine vision. Nonetheless, conventional semiconductor circuits encounter challenges in achieving ultra-fast processing speed and low power consumption due to their dissipative properties. Conversely, single flux quantum (SFQ) circuits exhibit inherent spiking behavior, showcasing their characteristics as a promising candidate for spiking neural networks (SNNs). In this work, we present a compact hybrid synapse circuit to mimic the biological interconnect functionality, enabling the weighting operations for excitatory and inhibitory impulses. Additionally, the proposed structure facilitates input accumulation, which is performed before the activation function. In the experiments, our synaptic structure interfaces with a soma circuit fabricated using a commercial Nb process, underscoring its compatibility and supporting its potential for integration into efficient neural network architectures. The weight value on the synapse is configurable by utilizing cryo-CMOS circuits, providing adaptability to the inference networks. We’ve successfully designed, fabricated, and partially tested the JJ-Synapse within our cryocooler system, enabling high-speed inference implementation for SNNs.

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Demonstration of superconducting memory for an RQL CPU

Cited by 5 publications

References 1 publication

Asynchronous Reversible Computing Unveiled Using Ballistic Shift Registers

Asynchronous Reversible Computing Unveiled Using Ballistic Shift Registers

BrainFreeze: Expanding the Capabilities of Neuromorphic Systems Using Mixed-Signal Superconducting Electronics

Hybrid synaptic structure for spiking neural network realization

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