Demonstration of Signal Transmission between Adiabatic Quantum-Flux-Parametrons and Rapid Single-Flux-Quantum Circuits Using Superconductive Microstrip Lines

China, Fumihiro; Tsuji, Naoki; Narama, Tatsuya; Takeuchi, Naoki; Ortlepp, Thomas; Yamanashi, Yuki; Yoshikawa, Nobuyuki

doi:10.1109/tasc.2016.2642046

Cited by 11 publications

(7 citation statements)

References 22 publications

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“…The design of the A2R interfaces is the same as that of the compact A2R interface shown in the literature [29], which can save the junction count and footprint compared to the original design [28]. The design of the R2A interfaces is based on that shown in the literature [28] but was slightly modified such that Iena can activate the R2A interface. Figure 3(a) depicts a simplified circuit diagram of the R2A interface used in the present study.…”

Section: A Deserializermentioning

confidence: 99%

“…First, we briefly describe the conventional SerDes for four-phase-clocked AQFP circuits, i.e., feedback-type SerDes. Then, we explain the details of the hybrid SerDes with a focus on the following two points: (i) The hybrid SerDes comprises RSFQ shift registers to facilitate the data storage during S2P and P2S conversion, with AQFP/RSFQ interfaces [28,29] transmitting data between the shift registers and the AQFP circuit under test (CUT). (ii) All the component circuits are seamlessly clocked by the identical excitation current, which facilitates the synchronization between the RSFQ and AQFP parts.…”

Section: Introductionmentioning

confidence: 99%

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Low-Latency Adiabatic Quantum-Flux-Parametron Circuit Integrated With a Hybrid Serializer/Deserializer

et al. 2022

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Adiabatic quantum-flux-parametron (AQFP) logic is an ultra-low-power superconductor logic family. AQFP logic gates are powered and clocked by dedicated clocking schemes using ac excitation currents to implement an energy-efficient switching process, adiabatic switching. We have proposed a lowlatency clocking scheme, delay-line clocking, and demonstrated basic AQFP logic gates. In order to test more complex circuits, a serializer/deserializer (SerDes) should be incorporated into the AQFP circuit under test, since the number of input/output (I/O) cables is limited by equipment. Therefore, in the present study we propose and develop a novel SerDes for testing delay-line-clocked AQFP circuits by combining AQFP and rapid single-flux-quantum (RSFQ) logic families, which we refer to as the AQFP/RSFQ hybrid SerDes. The hybrid SerDes comprises RSFQ shift registers to facilitate the data storage during serial-toparallel and parallel-to-serial conversion. Furthermore, all the component circuits in the hybrid SerDes are clocked by the identical excitation current to synchronize the AQFP and RSFQ parts. We fabricate and demonstrate a delay-line-clocked AQFP circuit (8-to-3 encoder, which is the largest delay-line-clocked circuit ever designed) integrated with the hybrid SerDes at 4.2 K up to 4.5 GHz. Our measurement results indicate that the hybrid SerDes enables the testing of delay-line-clocked AQFP circuits with only a few I/O cables and is thus a powerful tool for the development of very large-scale integration AQFP circuits.

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Section: A Deserializermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Low-Latency Adiabatic Quantum-Flux-Parametron Circuit Integrated With a Hybrid Serializer/Deserializer

et al. 2022

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“…1(c), generates a logic 1 (reset signal) when the input (flag bit) changes from 1 to 0, i.e., Iin decays. Then, the reset signal is sent to the voltage driver from the falling-edge detector via an AQFP/RSFQ interface [36]. The circuit parameters of the DC-SQUID stack in the current design are as follows.…”

Section: Aqfp/rsfq Hybrid Interfacementioning

confidence: 99%

Scalable readout interface for superconducting nanowire single-photon detectors using AQFP and RSFQ logic families

Takeuchi¹,

China²,

Miki³

et al. 2020

Opt. Express

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We propose a scalable readout interface for superconducting nanowire singlephoton detector (SSPD) arrays, which we call the AQFP/RSFQ interface. This interface is composed of adiabatic quantum flux parametron (AQFP) and rapid single flux quantum (RSFQ) logic families. The AQFP part reads out the spatial information of an SSPD array via a single cable, and the RSFQ part reads out the temporal information via a single cable. The hybrid interface has high temporal resolution owing to low timing jitter in the operation of the RSFQ part. In addition, the hybrid interface achieves high circuit scalability because of low supply current in the operation of the AQFP part. Therefore, the hybrid interface is suitable for handling many-pixel SSPD arrays. We demonstrate a four-pixel SSPD array using the hybrid interface as proof of concept. The measurement results show that the hybrid interface can read out all of the pixels with a low error rate and low timing jitter.

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“…It consists of superconducting chips with active logic and memory, mounted on a passive superconducting carrier. Superconducting energy-efficient logic families such as RQL [11] and ERSFQ [12] support direct transfer of ps data pulses on passive transmission line interconnects [13], [14] (AQFP technology requires costly energy conversion to RSFQ [15]). Flip-chip packaging with low resistance bumps [16], [17] means that there is no energy penalty to transfer data off-chip.…”

mentioning

confidence: 99%

Synchronous Chip-to-Chip Communication with a Multi-Chip Resonator Clock Distribution Network

Egan¹,

Nielsen²,

Strong³

et al. 2021

Preprint

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Superconducting digital circuits are a promising approach to build packaged-level integrated systems with high energy-efficiency and computational density. In such systems, performance of the data link between chips mounted on a multi-chip module (MCM) is a critical driver of performance. In this work we report a synchronous data link using Reciprocal Quantum Logic (RQL) enabled by resonant clock distribution on the chip and on the MCM carrier. The simple physical link has only four Josephson junctions and 3 fJ/bit dissipation, including a 300 W/W cooling overhead. The driver produces a signal with 35 GHz analog bandwidth and connects to a single-ended receiver via 20 Ω Nb Passive Transmission Line (PTL). To validate this link, we have designed, fabricated and tested two 32×32 mm 2 MCMs with eight 5×5 mm 2 chips connected serially and powered with a meander clock, and with four 10×10 mm 2 chips powered with a 2 GHz resonant clock. The meander clock MCM validates performance of the data link components, and achieved 5.4 dB AC bias margin with no degradation relative to individual chip test. The resonator MCM validates synchronization between chips, with a measured AC bias margin up to 4.8 dB between two chips. The resonator MCM is capable of powering circuits of 4 million Josephson junctions across the four chips with a projected 10 Gbps serial data rate. * This research is based upon work supported in part by the ODNI, IARPA, via ARO. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of the ODNI, IARPA, or the U.S. Government.

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Demonstration of Signal Transmission between Adiabatic Quantum-Flux-Parametrons and Rapid Single-Flux-Quantum Circuits Using Superconductive Microstrip Lines

Cited by 11 publications

References 22 publications

Low-Latency Adiabatic Quantum-Flux-Parametron Circuit Integrated With a Hybrid Serializer/Deserializer

Low-Latency Adiabatic Quantum-Flux-Parametron Circuit Integrated With a Hybrid Serializer/Deserializer

Scalable readout interface for superconducting nanowire single-photon detectors using AQFP and RSFQ logic families

Synchronous Chip-to-Chip Communication with a Multi-Chip Resonator Clock Distribution Network

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