Synchronous Chip-to-Chip Communication with a Multi-Chip Resonator Clock Distribution Network

Abstract

Superconducting digital circuits are a promising approach to build packaged-level integrated systems with high energy-efficiency and computational density. In such systems, performance of the data link between chips mounted on a multi-chip module (MCM) is a critical driver of performance. In this work we report a synchronous data link using Reciprocal Quantum Logic (RQL) enabled by resonant clock distribution on the chip and on the MCM carrier. The simple physical link has only four Josephson junctions and 3 fJ/bit dissipation, including a 300 W/W cooling overhead. The driver produces a signal with 35 GHz analog bandwidth and connects to a single-ended receiver via 20 Ω Nb Passive Transmission Line (PTL). To validate this link, we have designed, fabricated and tested two 32×32 mm 2 MCMs with eight 5×5 mm 2 chips connected serially and powered with a meander clock, and with four 10×10 mm 2 chips powered with a 2 GHz resonant clock. The meander clock MCM validates performance of the data link components, and achieved 5.4 dB AC bias margin with no degradation relative to individual chip test. The resonator MCM validates synchronization between chips, with a measured AC bias margin up to 4.8 dB between two chips. The resonator MCM is capable of powering circuits of 4 million Josephson junctions across the four chips with a projected 10 Gbps serial data rate. * This research is based upon work supported in part by the ODNI, IARPA, via ARO. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of the ODNI, IARPA, or the U.S. Government.

Isochronous Data Link Across a Superconducting Nb Flex Cable with 5 femtojoules per Bit

“…1 consists of a bandwidth-efficient driver, a 20 Ω line, and an oversampling receiver. The bandwidth-efficient driver is a self-resetting gate as described in [5]. The driver latches to produce a Gaussian waveform of about 10 underlying SFQ pulses per bit.…”

“…The receiver is DC-powered to guarantee that signal will be captured despite arbitrary timing relative to the RQL AC clock. The receiver consists simply of a two-junction Josephson transmission line with 35 µA and 50 µA critical currents as described in [5].…”

“…The "smcm4m" four Nb metal process supports the design of both 20 Ω data PTLs and the clock resonator network, isolated using a superconducting ground plane. The In bump bonding process, with 15 µm bump diameter, 35 µm bump pitch, and about 3 µm bump height post-bonding, supports MCM-to-chip transitions with 350 GHz analog bandwidth [5].…”

“…The 32×32 mm MCM carrier for the phase align experiments with both on-carrier PTL and Nb flex cable, contains two separate "megaZOR" resonator networks, with independent control of frequency and amplitude. Each MegaZOR is a resonator of λ/2 segments on the MCM designed to drive several on-chip ZOR resonators as described in [5]. The carrier MegaZOR design has been targeted to match the experimental average resonance frequency of the individual chips.…”

“…Nb interconnects having 700 GHz analog bandwidth can cover distance with appropriate data encoding and geometry of the wires [4]. A bandwidth-efficient driver producing 10 SFQ pulses per bit, with an analog bandwidth of 35 GHz and 0.58 fJ per bit has been reported in [5]. This bandwidth-efficient driver has been used to demonstrate synchronous communication between 10×10 mm chips on an MCM with interconnect length up to 54 mm.…”