Demonstration of scaled Ge p-channel FinFETs integrated on Si

Dal, M.J.H. van; Vellianitis, G.; Doornbos, G.; Duriez, B.; Shen, Ting; Wu, C.C.; Oxland, R.; Bhuwalka, K.K.; Holland, M.; Lee, T. L.; Wann, C.; Hsieh, C.H.; Lee, B. H.; Yin, K.M.; Zheng, Wei; Passlack, M.; Diaz, C.H.

doi:10.1109/iedm.2012.6479089

Cited by 42 publications

(25 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Most major semiconductor manufacturing companies and, moreover, the top semiconductor sales leaders in the high-end microprocessor market take high carrier mobility materials very seriously. A scan of high-profile device conferences or electron device literature can yield high-mobility material studies from major semiconductor manufacturers [122][123][124].…”

Section: Discussionmentioning

confidence: 99%

“…Alternatively, if narrow trenches are used, the defects can be captured by what is known as aspect-ratio-trapping (ART). As stated previously, van Dal et al reported scaled p-channel Ge MugFET devices with fin widths of 40 nm, fabricated on a Si bulk wafer using the ART technique [4,5].…”

Section: Substrates and Integrationmentioning

confidence: 99%

“…Feng et al fabricated Ge p-channel FinFETs with fin widths (W f in ) down to 130 nm [3]. Van Dal et al recently described scaled p-channel Ge FinFET devices with W f in of 40 nm, fabricated on a Si bulk wafer using the aspect-ratio-trapping technique, which will be discussed in the next section [4,5]. Liu et al reported p-type Ge FinFET devices with W f in = 60-100 nm and a summary of the best literature data for Ge FinFETs in terms of drive versus gate length [6].…”

Section: Highly Scaled Ge Fetsmentioning

confidence: 99%

See 2 more Smart Citations

Processing of germanium for integrated circuits

Duffy¹,

Shayesteh²,

Yu³

2014

Turk J Phys

View full text Add to dashboard Cite

Abstract:In this review paper the authors will focus on Ge processing for integrated circuits. The key areas that require the most attention are substrates and integration, gate dielectrics, and access resistance. We will discuss each of these topics in turn, while also reviewing the most scaled Ge field-effect-transistor devices, and consider how modelling activities have matured for Ge in recent years.

show abstract

Section: Discussionmentioning

confidence: 99%

Section: Substrates and Integrationmentioning

confidence: 99%

Section: Highly Scaled Ge Fetsmentioning

confidence: 99%

See 1 more Smart Citation

Processing of germanium for integrated circuits

Duffy¹,

Shayesteh²,

Yu³

2014

Turk J Phys

View full text Add to dashboard Cite

show abstract

“…In order to enhance future CMOS, Ge/III-V channel materials, which feature higher carrier mobility than Si, are currently being evaluated [1][2][3][4]. However, Ge/III-V MOS devices have been shown to have a high content of interface and oxide/border traps [5,6].…”

Section: Introductionmentioning

confidence: 99%

The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices

Vais

Martens

Franco

et al. 2015

2015 IEEE International Reliability Physics Symposium

View full text Add to dashboard Cite

In this paper, we present the results of a detailed study done on the correlation between frequency dispersion observed in AC admittance measurements and threshold voltage shifts observed in BTI reliability measurements on III-V MOS devices. We developed a detailed AC admittance model for MOS devices with border traps to study the effect of trap parameters on the AC admittance. We show, with the help of simulations and experiments, a clear correlation between border trap characteristics in AC admittance and BTI behavior. In addition, we propose a simplified and quick method to qualitatively characterize border traps using G/ as a measure for their density.

show abstract

“…Concurrently, germanium (Ge) has emerged as a strong candidate to maintain device performance at low operating voltages, 1 primarily owing to its superior carrier mobility and ease of integration into mainstream Si process flow. More recently, researchers have focused on the development of Ge-based electronic and optoelectronic devices, including: (i) Ge lasers on Si for on-chip integrated photonics; 2,3 (ii) high-speed and high-sensitivity Ge photoreceivers on Si 4,5 for optical data communication; (iii) Ge-based metal-oxide-semiconductor field-effect transistors (MOSFETs) for low-power logic; 6,7 (iv) Ge-based complementary-metal-oxide-semiconductor (CMOS) integrated circuits; 8 and (v) Ge-based quantum well fin field-effect transistors (FinFETs) [9][10][11] for next-generation high-speed, low-power logic applications. Thin epitaxial Ge layers have also been introduced as a buffer layer for developing GaAs solar cells on Si 12,13 and in hybrid IV/III-V multijunction solar cell configurations.…”

Section: Introductionmentioning

confidence: 99%

Growth, structural, and electrical properties of germanium-on-silicon heterostructure by molecular beam epitaxy

et al. 2017

View full text Add to dashboard Cite

The growth, morphological, and electrical properties of thin-film Ge grown by molecular beam epitaxy on Si using a two-step growth process were investigated. High-resolution x-ray diffraction analysis demonstrated ∼0.10% tensile-strained Ge epilayer, owing to the thermal expansion coefficient mismatch between Ge and Si, and negligible epilayer lattice tilt. Micro-Raman spectroscopic analysis corroborated the strain-state of the Ge thin-film. Cross-sectional transmission electron microscopy revealed the formation of 90 ° Lomer dislocation network at Ge/Si heterointerface, suggesting the rapid and complete relaxation of Ge epilayer during growth. Atomic force micrographs exhibited smooth surface morphology with surface roughness < 2 nm. Temperature dependent Hall mobility measurements and the modelling thereof indicated that ionized impurity scattering limited carrier mobility in Ge layer. Capacitance- and conductance-voltage measurements were performed to determine the effect of epilayer dislocation density on interfacial defect states (Dit) and their energy distribution. Finally, extracted Dit values were benchmarked against published Dit data for Ge MOS devices, as a function of threading dislocation density within the Ge layer. The results obtained were comparable with Ge MOS devices integrated on Si via alternative buffer schemes. This comprehensive study of directly-grown epitaxial Ge-on-Si provides a pathway for the development of Ge-based electronic devices on Si.

show abstract

Demonstration of scaled Ge p-channel FinFETs integrated on Si

Cited by 42 publications

References 8 publications

Processing of germanium for integrated circuits

Processing of germanium for integrated circuits

The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices

Growth, structural, and electrical properties of germanium-on-silicon heterostructure by molecular beam epitaxy

Contact Info

Product

Resources

About