Demodulators for a zero-if bluetooth receiver

IEEE Trans. Circuits Syst. I

et al. 2017

Abstract-Phase-domainAnalog-to-Digital Converters (Ph-ADCs) have been considered for power-efficient implementation of body-area network transceivers employing phase demodulation. Conventional implementations of the Ph-ADCs, which work based on a full-flash zero-crossing algorithm, use linear resistive/current combiners to determine the thermometer digital code of the signal phase. These architectures suffer from high-accuracy requirements, high-circuit complexity, and highpower consumption. Therefore, in this paper, a new IQ-assisted binary-search algorithm is proposed for implementing the Ph-ADC. The proposed Ph-ADC architecture avoids employing the power-hungry linear combiner. Moreover, for an N-bit Ph-ADC, the proposed algorithm requires only N+1 comparisons, whereas the conventional full-flash counterpart demands 2 N−1 comparisons. Based on the proposed architecture, two different 5-bit charge-redistribution Ph-ADCs are designed and one of them is fabricated in a standard 0.18-µm CMOS technology. The prototype achieves an ENOB of 4.85 bits at 1 MS/s, while dissipating 12.9 µW from a 1.2-V supply.Index Terms-Phase-domain analog-to-digital converter, IQ-assisted binary search, charge-redistribution Ph-ADC.

“…2. Schematic of the Ph-ADC implemented based on the full-flash algorithm using (a) resistive combiner [4] and (b) current combiner [10].…”

Section: Proposed Conversion Algorithmmentioning

confidence: 99%

Section: Proposed Conversion Algorithmmentioning

confidence: 99%

A Charge-Redistribution Phase-Domain ADC Using an IQ-Assisted Binary-Search Algorithm

Rajabi

Saberi

IEEE Trans. Circuits Syst. I

et al. 2017

“…The demodulation can be approximated as a coherent continuous phase index h = 0.32 FSK demodulation. Without co-channel interference, the bit error rate (BER) due to noise is given in [15] and shown to be approximately achievable with a zero-IF Bluetooth receiver in [16] …”

Section: Collision Analysis For Coexistence Of Multiple Bluetootmentioning

confidence: 99%

A Frequency Diversity Technique for Interference Mitigation in Coexisting Bluetooth and WLAN

2007 IEEE International Conference on Communications

2007

Co-channel interference has become an important problem with the increasing deployment of wireless networks in the unlicensed frequency band. Most existing schemes aim to avoid collisions on Bluetooth devices by modifying their hop sequences in the presence of WLAN interference. We propose a frequency diversity technique for Bluetooth, namely dual channel transmission (DCT), which reduces packet error rate (PER) due to co-channel interference when multiple Bluetooth piconets coexist with or without WLAN interference. The idea of DCT is to transmit the same packet on two distinct frequency hopped channels simultaneously and the power used in each channel is half of what would be used in single channel transmission (SCT). Since a packet is successfully received if at least one channel survives, the PER is reduced when multiple Bluetooth piconets coexist. Meanwhile, the two channels of DCT are separated by at least 22 MHz so that Bluetooth is also robust to WLAN interference. Theoretic analysis and numerical simulations show that PER for Bluetooth with DCT is significantly lower than that with SCT, when a small number of piconets coexist in the presence of WLAN interference. Comparisons to other collision avoidance mechanisms also demonstrate the effectiveness of DCT.

“…The fact that in FSK and PSK modulation schemes data information is encoded in the signal phase alone is utilized by the PhADC by only quantizing phase information as opposed to I and Q amplitude information, resulting in a compact and energy-efficient system architecture. Manuscript PhADC-based demodulators have proven to have bit-error-rate (BER) characteristics close to an ideal coherent GFSK demodulator [4]. PhADCs based on a zero-crossing conversion algorithm have been realized in silicon by a resistor-bridge-based approach [5], [6] as well as a current-mirror-based approach [7], [8].…”

Section: Introductionmentioning

confidence: 99%

A Comparative Analysis of Phase-Domain ADC and Amplitude-Domain IQ ADC

IEEE Trans. Circuits Syst. I

Lotfi

et al. 2015

A phase-domain analog-to-digital converter (PhADC) is a promising alternative to a pair of amplitude-domain in-phase and quadrature (IQ) ADCs for low power FSK/PSK demodulation, but the fundamental benefits and limitations of the PhADC over the IQ ADC have not been precisely quantified as yet. In this paper, analytical methods are proposed to comprehensively compare the PhADC and the IQ ADC. Phase signal-to-noise ratio (SNR) expressions of the two ADC types are formulated analytically to facilitate a quantitative comparison of them. In comparison with the IQ ADC, the PhADC is a more compact quantization and demodulation solution when interference accommodation is not required. Moreover, considering a flash ADC as an example of the low resolution (3-4 bit) IQ ADC, the PhADC has a lower theoretical energy limit than the flash ADC for a given phase ENOB. IQ offsets and amplitude mismatch impose unique nonlinearities on the PhADC due to the nonlinear amplitude-to-phase conversion. The understanding of this nonlinearity leads to a phase-domain mismatch and offset detection technique. Phase SNR is explicitly related to input noise for both ADCs, and to comparator offsets for the PhADC, respectively. All of the results prove that the PhADC is a promising quantization and demodulation solution.Index Terms-Amplitude mismatch, in-phase and quadrature (IQ) ADC, offset, phase-domain analog-to-digital converter (PhADC), phase nonlinearity, phase signal-to-noise ratio (SNR).