Delta Iddq for testing reliability

Powell, T.J.; Pair, Jarrell; John, M. St.; Counce, D.

doi:10.1109/vtest.2000.843876

Cited by 48 publications

(14 citation statements)

References 6 publications

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“…During test execution, real-time DUT response data collected by the tester is used as input to the limit setting algorithm, which calculates the appropriate limit on an individual die basis. Examples for Iddq are the ratio of maximum to minimum current ("current ratios" [31]), significant steps in the sorted currents ("current signatures", [16]) and changes in one vector to the next ("delta-I DDQ " [32]). Similar concepts were applied to MinV DD testing, where a predicted value of MinV DD was obtained from measurements of neighboring die and this value became the limit for the die under test [11].…”

Section: A Outlier Screens and Data Driven Testmentioning

confidence: 99%

Towards Variation-Aware Test Methods

Polian

Becker

Hellebrand

et al. 2011

2011 Sixteenth IEEE European Test Symposium

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Nanoelectronic circuits are increasingly affected by massive statistical process variations, leading to a paradigm shift in both design and test area. In circuit and system design, a broad class of methods for robustness like statistical design and self calibration has emerged and is increasingly used by the industry. The test community's answer to the massive-variation challenge is currently adaptive test. The test stimuli are modified on the fly (during test application) based on the circuit responses observed. The collected circuit outputs undergo statistical post-processing to facilitate pass/fail classification. We will present fundamentals of adaptive and robust test techniques and their theoretical background. While adaptive test is effective, the understanding how it covers defects under different process parameter combinations is not fully established yet with respect to algorithmic foundations. For this reason, novel analytic and algorithmic approaches in the field of variation-aware testing will also be presented in the tutorial. Coverage of defects in the process parameter space is modeled and maximized by an interplay between special fault simulation and multi-constrained ATPG algorithms. These systematic approaches can complement adaptive test application schemes to form a closed-loop system that combines analytical data with measurement results for maximal test quality. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE.

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Section: A Outlier Screens and Data Driven Testmentioning

confidence: 99%

Towards Variation-Aware Test Methods

Polian

Becker

Hellebrand

et al. 2011

2011 Sixteenth IEEE European Test Symposium

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show abstract

“…As the intrinsic leakage of CMOS transistors increases, the key to successfully implementing I DDQ testing is measuring signatures of the defective dies based on raw I DDQ values and developing screens for the dies with abnormal signatures. [4][5][6] Structural tests for screening frequency-dependent defects Transition delay faults commonly refer to frequencydependent defects that cause gross timing failures in core logic. Historically, manufacturers screened these faults using at-speed or high-speed functional device testing.…”

Section: W Robert Daaschmentioning

confidence: 99%

Obtaining high defect coverage for frequency-dependent defects in complex ASICs

Madge¹,

Benware²,

Daasch

2003

IEEE Des. Test. Comput.

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IN DEEP-SUBMICRON IC PROCESSES and products, traditional defect-based test methods using stuck-at test vectors and I DDQ patterns cannot sufficiently maintain quality and reliability goals, because of the increase of delay-sensitive (resistive) defects. Structural test methods based on path delay or rise and fall transitions can counteract this trend and avoid expensive functional testing.Frequency-dependent defects pose a significant challenge to IC suppliers. At-speed functional testing, which requires the generation of test patterns and the ATE to support them, is cost prohibitive. Moreover, suppliers must apply functional tests at the fully specified temperature and voltage ranges.For ASIC testing, structural test methods such as ATPG scan or BIST are generally accepted replacements for full at-speed testing, as long as several conditions are met: I The methods' stuck-at and delay fault coverage are at or above functional-test levels. I The fabrication process is controlled well within the modeled parametric specifications. I The on-chip IP (cores, memory, and I/O) is well characterized across worst-case PVT (process, voltage, and temperature).However, once manufacturers discard at-speed functional testing in favor of structural testing, testing's sole purpose becomes to screen defects, and therefore, the approach's success depends on high defect coverage. To fully realize high defect coverage and thus guarantee IC quality and reliability, designers must augment high fault coverage with additional defect-based screening methods. Defect screeningBoth defect-based test methods-such as transition delay fault (TDF) testing, minimum operating voltage (min V DD ), and very low voltage (VLV)-and temperature testing are important methods for screening resistive path and delay defects. 1-3 The major challenge for designers wanting to use these test methods is identifying and screening the defective dies in production without losing too many defect-free dies or consuming excessive amounts of test time in the search routines. Figures 1 and 2 give examples of resistive path defects as outliers in raw data collected from the ATE. Figure 1 plots the min V DD for two silicon wafer lots against process speed, which we measured with a process monitor. Although correlated to the part's operating frequency, min V DD does not measure the operating frequency of the device under test. Most dies in each lot show the expected intrinsic behavior of a higher min V DD as the process slows; however, outliers to the intrinsic distribution show a higher min V DD than expected for the measured process speed. Clearly, applying a single volt-

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“…Other than that, a pass/fail threshold is determined through the statistical post processing of measured IDDQ currents in these methods. For example, in [3]- [5], delta-IDDQ, which compares differences between IDDQ currents in an IDDQ signature, and its extensions have been introduced. In [6], current ratio, which uses a ratio of maximum and minimum IDDQ currents for the pass/fail threshold is presented.…”

Section: Introductionmentioning

confidence: 99%

IDDQ Outlier Screening through Two-Phase Approach: Clustering-Based Filtering and Estimation-Based Current-Threshold Determination

Shintani

Satō

2014

IEICE Trans. Inf. & Syst.

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SUMMARYWe propose a novel IDDQ outlier screening flow through a two-phase approach: a clustering-based filtering and an estimation-based current-threshold determination. In the proposed flow, a clustering technique first filters out chips that have high IDDQ current. Then, in the current-threshold determination phase, device-parameters of the unfiltered chips are estimated based on measured IDDQ currents through Bayesian inference. The estimated device-parameters will further be used to determine a statistical leakage current distribution for each test pattern and to calculate a and suitable current-threshold. Numerical experiments using a virtual wafer show that our proposed technique is 14 times more accurate than the neighbor nearest residual (NNR) method and can achieve 80 % of the test escape in the case of small leakage faults whose ratios of leakage fault sizes to the nominal IDDQ current are above 40 %.

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Delta Iddq for testing reliability

Cited by 48 publications

References 6 publications

Towards Variation-Aware Test Methods

Towards Variation-Aware Test Methods

Obtaining high defect coverage for frequency-dependent defects in complex ASICs

IDDQ Outlier Screening through Two-Phase Approach: Clustering-Based Filtering and Estimation-Based Current-Threshold Determination

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