Delay insensitive system-on-chip interconnect using 1-of-4 data encoding

Bainbridge, W.J.; Furber, Steve

doi:10.1109/async.2001.914075

Cited by 81 publications

(32 citation statements)

References 6 publications

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“…Although the asynchronous communication links have been proposed [4]- [8], a large number of wires and communication steps are required for an asynchronous handshake operation, where data is locally synchronized by using a request and an acknowledge signals. To reduce the overhead of the asynchronous operation, high-speed and wireefficient asynchronous communication links based on onephase signalling have been reported [9], [10].…”

Section: Introductionmentioning

confidence: 99%

Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link

Onizawa

Hanyu

2010

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper presents highly reliable multiple-valued onephase signalling for an asynchronous on-chip communication link under process, supply-voltage and temperature variations. New multiple-valued dual-rail encoding, where each code is represented by the minimum set of three values, makes it possible to perform asynchronous communication between modules with just two wires. Since an appropriate current level is individually assigned to the logic value, a sufficient dynamic range between adjacent current signals can be maintained in the proposed multiple-valued current-mode (MVCM) circuit, which improves the robustness against the process variation. Moreover, as the supply-voltage and the temperature variations in smaller dimensions of circuit elements are dominated as the common-mode variation, a local reference voltage signal according to the variations can be adaptively generated to compensate characteristic change of the MVCM-circuit component. As a result, the proposed asynchronous on-chip communication link is correctly operated in the operation range from 1.1 V to 1.4 V of the supply voltage and that from −50 • C to 75 • C under the process variation of 3σ. In fact, it is demonstrated by HSPICE simulation in a 0.13-μm CMOS process that the throughput of the proposed circuit is enhanced to 435% in comparison with that of the conventional 4-phase asynchronous communication circuit under a comparable energy dissipation.

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Section: Introductionmentioning

confidence: 99%

Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link

Onizawa

Hanyu

2010

IEICE Trans. Inf. & Syst.

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“…Alternatively, an asynchronous data link employs handshake instead of clocks. Traditional asynchronous protocols are relatively slow due to the need to acknowledge transitions [11], [12]. In [13], asynchronous protocols share data lines, but their performance depends on wire delays.…”

Section: Introductionmentioning

confidence: 99%

Asynchronous Current Mode Serial Communication

Dobkin

Moyal

Kolodny

et al. 2010

IEEE Trans. VLSI Syst.

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Abstract-An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the differential level encoded dual-rail (LEDR) two-phase asynchronous protocol, avoiding per-bit handshake and eliminating per-bit synchronization, in contrast with synchronous serial links that rely on complex clock recovery. Novel low-power current signaling driver and receiver circuits are presented, enabling high-speed communication at a very low voltage swing over long wires. In contrast, previous methods employed voltage sensing, resulting in higher swing, higher dynamic power, shorter wires or slower operation. The asynchronous current mode driver is designed to support varying data rates, and it eliminates the need for balanced codes and busy toggling that prevent deep discharge. The data cycle time of the link is equal to a single gate delay, enabling 67 Gb/s throughput in 65-nm technology. Wave-pipelining is employed also by the asynchronous SERDES circuits, to enable such high speed operation. The link was SPICE simulated for 65-nm technology, using wire models obtained by a 3-D EM solver. The link incurs lower power and area relative to synchronous and asynchronous bit-parallel communications, and these relative benefits also scale with technology.

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“…Unlike our work the Nexus crossbar is based on custom designed pre-charge domino logic. Work by Bainbridge and Furber has also been based on a 1-of-4, 4-phase approach [4]. Again, unlike our work their work requires a sequential cell that does not exist in normal standard cell libraries (a Celement) and does not make use of circuit optimization from commercial CAD tools.…”

Section: Related Workmentioning

confidence: 99%

“…Our initial designs were based on a 1-of-4, 4-phase protocol since this implementation has been commonly used in previous work on asynchronous interconnect [4,5]. However, the throughput restrictions of the 4-phase handshaking prevented any of our 4-phase designs from performing at a speed equal to that which could be easily achieved using a synchronous interconnect without any pipelining.…”

Section: Designmentioning

confidence: 99%

“…Although register pipelining increases throughput, there is a significant design effort required to implement these synchronous pipeline stages since each individual register requires a low-skew clock. Asynchronous techniques have been suggested as a potential solution to the problem of IC interconnect [4,5]. These asynchronous techniques do not require a global clock.…”

Section: Introductionmentioning

confidence: 99%

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