Delay fault models for VLSI circuits

Pomeranz, Irith; Reddy, S.M.

doi:10.1016/s0167-9260(98)00019-4

Cited by 4 publications

(2 citation statements)

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“…Test generation for path delay faults is known to be computationally intensive as the number of paths in a circuit can be exponential with respect to the circuit size. Path delay fault test can be broadly classified into two categories, namely, robust delay fault test and nonrobust delay fault test [Gharaybeh et al 1997;Pomeranz and Reddy 1998]. Robust path delay fault tests [Fuchs et al 1993;McGeer et al 1991;Saldanha et al 1992] are those which can detect faults along a path irrespective of any other faults in the circuit.…”

Section: Introductionmentioning

confidence: 99%

Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay Faults

Mondal

Chakrabarti

Dasgupta

2012

ACM Trans. Des. Autom. Electron. Syst.

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We present a symbolic-event-propagation-based scheme to generate hazard-free tests for robust path delay faults. This approach identifies all robustly testable paths in a circuit and the corresponding complete set of test vectors. We address the problem of finding a minimal set of test vectors that covers all robustly testable paths. We propose greedy and simulated-annealing-based algorithms to find the same. Results on ISCAS89 benchmark circuits show a considerable reduction in test vectors for covering all robustly testable paths.

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Section: Introductionmentioning

confidence: 99%

Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay Faults

Mondal

Chakrabarti

Dasgupta

2012

ACM Trans. Des. Autom. Electron. Syst.

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“…Therefore circuits are tested for functional and temporal behavior. One very powerful fault model is the Path Delay Fault Model (PDFM) that allows to detect static and dynamic faults [7].…”

Section: Introductionmentioning

confidence: 99%