Delay-Driven and Antenna-Aware Layer Assignment in Global Routing Under Multitier Interconnect Structure

Abstract

A multilayer routing system usually adopts multiple interconnect configuration with different wire sizes and thicknesses. Since thicker layers of metal lead to fatter wires with smaller resistance, the layer assignment (LA) of nets has a large impact on the interconnect delay. However, such layer-dependent characteristics have been ignored by most of the state-of-the-art academic LA methods. These characteristics also weaken the previous wire length-based antenna avoidance method, because the net length itself cannot accurately capture the antenna area under the condition of various wire sizes. To remedy this deficiency, this paper proposes a more effective three-stage LA algorithm under multitier interconnect structure, and focuses on minimizing delays, via count, and antenna violations. It first minimizes the total delay and via count simultaneously by dynamic programming and negotiation technique, and then further minimizes the maximum delay carefully while almost unchanging the via count. After that, a check-and-repair method is adopted to further fix the antenna violations. The experimental results on the International Conference on Computer-Aided Design'09 benchmarks show that the proposed algorithm can significantly reduce the total delay and maximum delay while still keeping roughly the same via count compared with the state-of-the-art via count minimization LA method negotiation-based via minimization algorithm. At the same time, the antenna violation repair method can dramatically reduce the antenna violated nets and sinks with little impact on the solution quality. Index Terms-Antenna effect, delay optimization, global routing (GR), layer assignment (LA), multitier interconnect structure, via minimization.0278-0070 . His current research interests include very large scale integration physical design, system on chip design and packaging, optimization algorithm and its application, and application specific architecture design and chip design. Jianchang Ao received the B.S. degree from South He is currently with EDA Laboratory, Tsinghua University. His current research interests include algorithms for very large scale integration physical design, especially routing. Fuqi Luo received the B.S. degree from Chongqing University, Chongqing, China, in 2006. He is currently pursuing the master's degree with Tsinghua University, Beijing, China, both in computer science and technology.His current research interests include algorithms for very large scale integration physical design, especially global routing and printed circuit board routing.