Delay and power expressions characterizing a CMOS inverter driving an RLC load

Tang, K.T.; Friedman, Eby G.

doi:10.1109/iscas.2000.856052

Cited by 19 publications

(12 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…(2), which in turn accounts for the short-channel effects of the transistors. In contrast to other delay estimates published recently in [16] and [17], Eq. (15) provides a simple expression that relates the inverter delay to load impedance as well as the device parameters such as β n(p) and device threshold voltage V T .…”

Section: Optimizationcontrasting

confidence: 61%

“…The input to the inverter is a flattened ramp input with a rise-time varying between 80psec and 500psec. The delay of this inverter is calculated using four different approaches: HSPICE simulation, delay expression proposed in [18], the delay expression proposed in [17], and Eq. (12).…”

Section: Optimizationmentioning

confidence: 99%

“…By reducing the input transition time, the ground bounce peak amplitude increases as indicated from Eq. (17). Larger amplitudes of the ground bounce reduces the current capability of the MOS devices and consequently results in an increase in the propagation delay of the multi-stage buffer.…”

Section: Optimizationmentioning

confidence: 99%

See 2 more Smart Citations

Ground bounce in digital VLSI circuits

Heydari

Pedram

2003

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Abstract-This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the propagation delay and the optimum tapering factor of a multistage buffer is discussed and a mathematical relationship for total propagation delay in the presence of the ground bounce is obtained. Effect of an on-chip decoupling capacitor on the ground bounce waveform and circuit speed is analyzed next and a closed form expression for the peak value of the differential-mode component of the ground bounce in terms of the on-chip decoupling capacitor is provided. Finally a design methodology for controlling the switching times of the output drivers to minimize the ground bounce is presented.

show abstract

Section: Optimizationcontrasting

confidence: 61%

Section: Optimizationmentioning

confidence: 99%

See 1 more Smart Citation

Ground bounce in digital VLSI circuits

Heydari

Pedram

2003

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

show abstract

“…Different techniques have been developed to characterize under different load models. The general form of (2) is valid whether the load is modeled as a capacitive load [28], a lossless transmission line [29], or a lossy transmission line [30]. is also a function of ; however, the dependence of on is small.…”

Section: B Transient Power Of Inductive Linesmentioning

confidence: 99%

“…A lumped model is widely used as a simple reduced order model for inductive interconnects [1], [30], [38]- [43]. The total line resistance, capacitance, and inductance are , , and , respectively, where is the line length.…”

Section: Appendix Transition Time For a Signal At The Far End Of An Imentioning

confidence: 99%

Power characteristics of inductive interconnect

El-Moursy

Friedman

10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003

Self Cite

View full text Add to dashboard Cite

Abstract-The width of an interconnect line affects the total power consumed by a circuit. The effect of wire sizing on the power characteristics of an inductive interconnect line is presented in this paper. The matching condition between the driver and the load affects the power consumption since the short-circuit power dissipation may decrease and the dynamic power will increase with wider lines. A tradeoff, therefore, exists between short-circuit and dynamic power in inductive interconnects. The short-circuit power increases with wider linewidths only if the line is underdriven. The power characteristics of inductive interconnects therefore may have a great influence on wire sizing optimization techniques. An analytic solution of the transition time of a signal propagating along an inductive interconnect with an error of less than 15% is presented. The solution is useful in wire sizing synthesis techniques to decrease the overall power dissipation. The optimum linewidth that minimizes the total transient power dissipation is determined. An analytic solution for the optimum width with an error of less than 6% is presented. For a specific set of line parameters and resistivities, a reduction in power approaching 80% is achieved as compared to the minimum wire width. Considering the driver size in the design process, the optimum wire and driver size that minimizes the total transient power is also determined.Index Terms-Characteristic impedance, dynamic power, inductive interconnect, short-circuit power, transient power dissipation, underdamped systems.

show abstract