Degree Conditions for Fractional $$(g,f,n',m)$$ ( g , f , n ′ , m ) -Critical Deleted Graphs and Fractional ID-(g, f, m)-Deleted Graphs

Abstract

A graph G is called a fractional (g, f, n , m)-critical deleted graph if after deleting any n vertices of G the remaining graph is a fractional (g, f, m)-deleted graph. A graph G is called a fractional ID-(g, f, m)-deleted graph if after deleting any independent set I of G the remaining graph is a fractional (g, f, m)-deleted graph. In this paper, we give some sharp degree conditions for a graph to be a fractional (g, f, n , m)-critical deleted graph and a fractional ID-(g, f, m)-deleted graph. The tight degree conditions for fractional (a, b, n , m)-critical deleted graphs and fractional ID-(a, b, m)-deleted graphs are also considered.

The Extension Degree Conditions for Fractional Factor

“…Note that Lemma 3 and Corollary 2 here are the extension results for the corresponding conclusions in Gao et al [6].…”

“…The following results in fractional ID-(g, f, m)-deleted setting as second part of main conclusions which are the extension of Theorem 4, Theorem 5 and Theorem 6 showed in Gao et al [6], respectively.…”

“…The proof of complete graph setting is done. ✷ Clearly, Lemma 2 is the extension of previous conclusion on the complete graph marked in Lemma 2 of Gao et al [6]. By setting n ′ = 0 in Lemma 2, the corollary present below will be employed in Section 3.…”

“…Using the consideration in Subsection 2.1, (5) holds as well. In light of (5), (6), n > (b+a−2+2m)(b+a)…”

Single‐Cell Stateful Logic Using a Dual‐Bit Memristor

“…There have been non-stateful (or stateless) logic methods that achieved the logic functions in a single cell in the memristor crossbar array utilizing the bipolar resistance switching (BRS) device or symmetric or asymmetric complementary resistance switching (CRS) device. [19][20][21][22][23] In those methods, the input data are input from the controller to the memristor as a voltage form, and the output data are recorded to the memristor as a resistance form. Therefore, its data control and manipulation processes are completely different from the stateful logic device, and thus, these technologies should be dealt with separately.…”