Degradation of III–V inversion-type enhancement-mode MOSFETs

Effects of channel hot carrier stress on III–V bulk planar MOSFETs

“…It is interesting to compare this result with what we found in [37]- [38] with a staircase gate stress. In fact, in [37]- [38], dielectric breakdown occurred only when the gate-to-source voltage was higher than 3.8V, corresponding to a dielectric field almost 3 times higher. Also, other authors reported much higher Al 2 O 3 breakdown fields [39]- [41].…”

“…Nonetheless, there are many differences with respect the previous works. In fact: 1) In [37]- [38], there was almost no drain-to-source current during the stress, while, in this work, a current as high as 3 mA flows through the channel, and hot electrons are generated (CHC stress). Hot electrons can damage the device near the drain if adequate countermeasures are not employed [31]- [34].…”

“…2) In [37]- [38] the stress time was considerably shorter than that used in this work. Therefore, it's reasonable that much higher gate-to source voltages were required to induce a dielectric breakdown in such a short time.…”

“…In this way, holes might be accelerated and induce damage near the source. In the literature there are some works on conventional silicon MOSFETs, which investigated the accelerated oxide breakdown induced by CHC [36]- [37]. In these works, the gate and drain bias voltages allowed not only hot carrier generation but also injection in the oxide, because the electron energy overwhelmed the conduction band offset, and there was a positive gate to drain voltage.…”

Reliability of High-Mobility InGaAs Channel n-MOSFETs Under BTI Stress

“…In order to clarify this issue, the ΔI off s -V d curves measured after 500 s stress and 500 s recovery were conducted. If ΔI off s is due to the change of surface potential pinning [35], [36], ΔI off s should be the diffusion current of minority carriers in the SS region satisfying the following equation [22]:…”