Degradation Mechanisms of GaN HEMTs With p-Type Gate Under Forward Gate Bias Overstress

Abstract

This paper investigates the degradation of GaN-based HEMTs with p-type gate submitted to positive gate bias stress. Based on combined electrical and optical testing, we demonstrate the existence of different degradation processes, depending on the applied stress voltage V Gstress : 1) for V Gstress < 7 V, no significant degradation is observed, thus demonstrating a good stability of the analyzed technology; 2) for 7 V < V Gstress < 11.5 V, a negative shift in threshold voltage (V th ) is observed, well correlated with a decrease in the gate leakage current and of the luminescence signal associated with hole injection. The negative V th shift is ascribed to the trapping of holes in the AlGaN and/or p-GaN/AlGaN interface; and 3) for V Gstress ≥ 12 V, threshold voltage recovers its initial value. This is ascribed to a net-negative charge, generated either by the trapping of electrons injected from the 2-D electron gas to the AlGaN or to the de-trapping of the holes injected in 2). The results described within this paper provide relevant information for understanding the degradation dynamics of normally off GaN transistors submitted to extremely high gate voltage levels far beyond maximum use.

Characterizing Threshold Voltage Shifts and Recovery in Schottky Gate and Ohmic Gate GaN HEMTs

“…The first and most obvious analysis is that in the case of the Ohmic Gate GaN HEMT the resulting VTH shift after stress is negative and the peak shift increases with increasing stress, with a peak shift of -2.5% for the low current stress and -4% for the high current stress. Minor negative shifts for this gate contact technology at this stress levels were also reported in [30].…”

Stability and Reliability of Lateral GaN Power Field-Effect Transistors

“…In this regime, I G tends to increase with time as hole accumulation at the p-GaN/AlGaN interface reduces the energy barrier presented by the AlGaN to further electron injection from the 2DEG [138]. 3) Depletion of holes within the p-GaN layer inducing a positive V T shift [134], [135], [140]. High V G stress eventually induces permanent degradation, as discussed below.…”

On the Challenges of Reliable Threshold Voltage Measurement in Ohmic and Schottky Gate p-GaN HEMTs

“…Among various normally off HEMT architectures p-GaN gate AlGaN/GaN-on-Si structures have gained considerable commercial traction and studies are underway to understand and engineer an optimum, reliable gate stack [3][4] [5]. Threshold voltage (V th ) instabilities are consistently reported under on/off state operational stress [6] and are often attributed to the charge imbalance created in the p-GaN region [7] [8] or AlGaN region [9][10] [11] of the gate stack. The charge imbalance is caused by trapping or detrapping of electrons or holes in these layers.…”