Degradation and breakdown of 0.9 nm EOT SiO/sub 2/ ALD HfO/sub 2/metal gate stacks under positive constant voltage stress

Abstract

By means of leakage current measurements, charge pumping and TDDB analysis, we construct a consistent model for the degradation and breakdown of 0.9 nm EOT Atomic Layer Deposited (ALD) HfO 2 . During degradation, traps and two-trap clusters are formed in the HfO 2 giving rise to considerable SILC. The two-trap clusters subsequently wear out, finally leading to an abrupt hard breakdown. We demonstrate that 0.9 nm EOT ALD HfO 2 is intrinsically reliable under Constant Voltage Stress if hard breakdown is used as a failure criterion.

The “buffering” role of high-к in post breakdown degradation immunity of advanced dual layer dielectric gate stacks

“…Up to now, the sequence of breakdown has remained a mystery with contradicting results and no unified understanding to leverage on. While some groups suggest HK to be the first to breakdown [21] - [23], others indicate IL to be the weakest link [24] - [30]. Without having a universal understanding on the breakdown sequence, it is difficult to proceed further in analyzing the post-BD phase of degradation.…”

Physically unclonable function using CMOS breakdown position

“…It can be clearly observed that the Weibull-slope (β) increases with elevated stress voltages. We attribute the variations on slopes to the competition of breakdown in a bilayer dielectric stack, consisting of SiO 2 and high-k [20]- [21]. Note that the traditional Weibull fitting is not applicable with this varying slopes, and the limited number of samples is not sufficient to characterize the bimodal distribution.…”

Time dependent dielectric breakdown and stress induced leakage current characteristics of 8Å EOT HfO<inf>2</inf> N-MOSFETS

“…Note however that the current in the region of the fit is in the micro-amp range, suggesting that 2-trap conduction is already dominant. If this is the case then, as shown by Degraeve et al [10], the SILC generation rate would be twice the TDDB trap generation rate.…”

“…To further investigate the possibility of a high defect generation rate in these devices we examined the I-t traces during stress. It has been shown that subtracting the initial charging component from the I-t trace, the pure leakage during the stress can be extracted [10]. This is shown in figure 4a for the SiGe devices.…”