Definition of an innovative filling structure for digital blocks : the DFM filler cell

Remy, Laurent; Coll, Philippe; Picot, F.; Mico, Philippe; Portal, Jean‐Michel

doi:10.1109/icecs.2009.5410922

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“…Recently, commercial P&R tools have claimed that minimum implant area rules are considered during the implementation, given that filler cells with active layers can be used to improve active density and manage STI stress effects [15]. Commercial P&R tools apparently fix the minimum implant area violations by inserting filler cells at the final design stage.…”

Section: Introductionmentioning

confidence: 99%

Minimum implant area-aware gate sizing and placement

Kahng

Lee

2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

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With reduction of minimum feature size, the minimum implant area (MinIA) constraint is emerging as a new challenge for the physical implementation flow in sub-22nm technology. In particular, the MinIA constraint induces a new problem formulation wherein gate sizing and V t -swapping must now be linked closely with detailed placement changes. To solve this new problem, we propose heuristic methods that fix MinIA violations and reduce power with gate sizing while minimizing placement perturbation to avoid creating extra timing violations. Compared to recent versions of commercial P&R tools, our methodologies achieve significant reductions (up to 100%) in the number of MinIA violations under timing/power constraints.

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Section: Introductionmentioning

confidence: 99%