Defense Against on-Chip Trojans Enabling Traffic Analysis Attacks

Ahmed, M Meraj; Dhavlle, Abhijitt; Mansoor, Naseef; Sutradhar, Purab Ranjan; Dinakarrao, Sai Manoj Pudukotai; Basu, Kanad; Ganguly, Amlan

doi:10.1109/asianhost51057.2020.9358250

Cited by 5 publications

(9 citation statements)

References 18 publications

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“…Ahmed et al [4] proposed a lightweight and naive HT that can leak traffic patterns to an adversary so that the adversary can do traffic analysis. The HT is capable of the naive task of periodically counting number of packets in a time window and leak that information to the adversary.…”

Section: Electrical Linksmentioning

confidence: 99%

“…After stealing information, the HT will packetize and transfer the information to remote attacker for further processing. Similar to [4], the attacker uses a ML technique, specifically an artificial neural network, to infer properties of application running on the system and reverse engineer the architectural design. The authors shows that it can reveal information such as router micro-architecture, cache organization, processor platform, and NoC configurations.…”

Section: Electrical Linksmentioning

confidence: 99%

“…A Simulated Annealing based randomized routing mechanism is proposed by [4] to overcome traffic analysis attack. Since a fully randomized routing degrades performance of NoC, the authors used parameterized Simulated Annealing that can balance between security against traffic analysis and performance.…”

Section: Confidentialitymentioning

confidence: 99%

“…This method reduces the user profile identification accuracy from 98% to 15%. An attack proposed by [3] has the similar basic intuition as [4]. Therefore, the solution presented by [3] to overcome ML-based attacks on eavesdropped data can be used.…”

Section: Confidentialitymentioning

confidence: 99%

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Security of Electrical, Optical and Wireless On-Chip Interconnects: A Survey

Weerasena¹,

Mishra²

2023

Preprint

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The advancement of manufacturing technologies has enabled the integration of more intellectual property (IP) cores on the same system-on-chip (SoC). Scalable and high throughput on-chip communication architecture has become a vital component in today's SoCs. Diverse technologies such as electrical, wireless, optical, and hybrid are available for on-chip communication with different architectures supporting them. Security of the on-chip communication is crucial because exploiting any vulnerability would be a goldmine for an attacker. In this survey, we provide a comprehensive review of threat models, attacks and countermeasures over diverse on-chip communication technologies as well as sophisticated architectures.CCS Concepts: • Hardware → Network on chip; • Security and privacy → Hardware security implementation.

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Section: Electrical Linksmentioning

confidence: 99%

Section: Electrical Linksmentioning

confidence: 99%

Section: Confidentialitymentioning

confidence: 99%

Section: Confidentialitymentioning

confidence: 99%

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Security of Electrical, Optical and Wireless On-Chip Interconnects: A Survey

Weerasena¹,

Mishra²

2023

Preprint

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“…In our attack model, we assume one or more NoC switches in the system to be infected with the HT. While research has proposed the design of HTs to count the number of packets, such as the one in [23], reading the destination is a new design concept. The HT design proposed in [23] uses one counter per switch and tallies the total packets through the infected switch.…”

Section: Hardware Trojan (Ht) Designmentioning

confidence: 99%

Address Obfuscation to Protect against Hardware Trojans in Network-on-Chips

Mountford,

Dhavlle,

Tevebaugh

et al. 2023

JLPEA

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In modern computing, which relies on the interconnection of networks used in many/multi-core systems, any system can be critically subverted if the interconnection is compromised. This can be done in a multitude of ways, but the threat of a hardware Trojan (HT) being injected into a system is particularly prevalent due to the increase in third-party manufacturers for system-on-chip (SoC) designs. With a local injection of an HT in an SoC, an adversary can gain access to information about applications running on the system by revealing specific communications of the SoC, and the network-on-chip (NoC) as a whole. This heavily compromises the system and gives information to the attacker, which can lead to more tailored, compromising attacks. In this paper, we demonstrate an HT that exploits communication patterns inside an SoC to reveal applications that are running on an NoC with multi/many-core processors. This is performed by leaking packet counts, after which the attacker then uses machine learning techniques to identify applications running on processors, and the SoC as a whole. We also propose a LUT-based obfuscation technique to limit the information available to the hardware Trojan. Our results indicate that this obfuscation method can reduce the accuracy of this attack from 99% to <8% in multi/many-core systems.

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Design of Hardware Trojans and its Impact on CPS Systems: A Comprehensive Survey

Dhavlle

Hassan

Mittapalli

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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The ever-increasing demand for sophisticated cyberphysical systems (CPS), combined with the fabless model, led to vulnerability exploits in the IC supply chain, especially the insertion of hardware Trojans (HTs). The HTs are malicious modifications made to an authentic design to disrupt the functioning of the integrated circuits (ICs). In this work, we present a survey of the state-of-the-art HT designs focusing on the Trojan design, the risk level in the supply chain, and the targeted platform, followed by a discussion based on our observations. We categorize the HT designs based on the targeted platforms such as ML accelerators, IoT devices, FPGAs, ASICs, memory devices, CPU, and Cryptographic cores.

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Defense Against on-Chip Trojans Enabling Traffic Analysis Attacks

Cited by 5 publications

References 18 publications

Security of Electrical, Optical and Wireless On-Chip Interconnects: A Survey

Security of Electrical, Optical and Wireless On-Chip Interconnects: A Survey

Address Obfuscation to Protect against Hardware Trojans in Network-on-Chips

Design of Hardware Trojans and its Impact on CPS Systems: A Comprehensive Survey

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