Defect state passivation at III-V oxide interfaces for complementary metal–oxide–semiconductor devices

Robertson, John; Guo, Yuzheng; Lin, Liang

doi:10.1063/1.4913832

Cited by 86 publications

(51 citation statements)

References 85 publications

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“…5,6,9 As pointed by Robertson et al, though a perfect trivalent oxide/GaAs interface is free of gap states, the presence of specific interface defects, As-As dimers, and dangling bonds of Ga and As contributes to the formation of important gap states. [10][11][12][13][14] This understanding strongly suggests that the elimination or passivation of these defect states is mandatory to bring out superior transport properties of GaAs. One solution is the use of an ultra-high vacuum (UHV) process, whereby both III-V epitaxy and dielectric deposition are performed under UHV.…”

Section: -2 Aoki Et Almentioning

confidence: 99%

“…[48][49][50] Introduction of the AlN passivation led to the incorporation of nitrogen at the interface as shown in Figure 6. Guo et al proposed a nitrogen passivation mechanism, 38,13 whereby nitrogen at the Al 2 O 3 /GaAs interface can replace interfacial arsenic (As), leading to the efficient removal of problematic As dimers or As-dangling bond states. This mechanism was experimentally confirmed in the case of In 0.53 Ga 0.47 As.…”

Section: Characterization Of Electrical Properties Of Al 2 O 3 / Amentioning

confidence: 99%

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Electrical properties of GaAs metal–oxide–semiconductor structure comprising Al2O3 gate oxide and AlN passivation layer fabricated in situ using a metal–organic vapor deposition/atomic layer deposition hybrid system

et al. 2015

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This paper presents a compressive study on the fabrication and optimization of GaAs metal–oxide–semiconductor (MOS) structures comprising a Al2O3 gate oxide, deposited via atomic layer deposition (ALD), with an AlN interfacial passivation layer prepared in situ via metal–organic chemical vapor deposition (MOCVD). The established protocol afforded self-limiting growth of Al2O3 in the atmospheric MOCVD reactor. Consequently, this enabled successive growth of MOCVD-formed AlN and ALD-formed Al2O3 layers on the GaAs substrate. The effects of AlN thickness, post-deposition anneal (PDA) conditions, and crystal orientation of the GaAs substrate on the electrical properties of the resulting MOS capacitors were investigated. Thin AlN passivation layers afforded incorporation of optimum amounts of nitrogen, leading to good capacitance–voltage (C–V) characteristics with reduced frequency dispersion. In contrast, excessively thick AlN passivation layers degraded the interface, thereby increasing the interfacial density of states (Dit) near the midgap and reducing the conduction band offset. To further improve the interface with the thin AlN passivation layers, the PDA conditions were optimized. Using wet nitrogen at 600 °C was effective to reduce Dit to below 2 × 1012 cm−2 eV−1. Using a (111)A substrate was also effective in reducing the frequency dispersion of accumulation capacitance, thus suggesting the suppression of traps in GaAs located near the dielectric/GaAs interface. The current findings suggest that using an atmosphere ALD process with in situ AlN passivation using the current MOCVD system could be an efficient solution to improving GaAs MOS interfaces.

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Section: -2 Aoki Et Almentioning

confidence: 99%

Section: Characterization Of Electrical Properties Of Al 2 O 3 / Amentioning

confidence: 99%

Electrical properties of GaAs metal–oxide–semiconductor structure comprising Al2O3 gate oxide and AlN passivation layer fabricated in situ using a metal–organic vapor deposition/atomic layer deposition hybrid system

et al. 2015

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“…[8][9][10][11][12][13] In addition to these interfacial states, a high density of oxide traps (D ot ) has recently been detected in the oxide layer of metal-oxide-semiconductor (MOS) devices. Capacitancevoltage (CV) measurements show a bimodal distribution for the density of defect states in the oxide, 14 with one peak at 1.5 eV above and the other at 0.5 eV below the CBM of InGaAs.…”

mentioning

confidence: 99%

Nature of electron trap states under inversion at In0.53Ga0.47As/Al2O3 interfaces

Colleoni

Pourtois

Pasquarello

2017

Applied Physics Letters

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In and Ga impurities substitutional to Al in the oxide layer resulting from diffusion out of the substrate are identified as candidates for electron traps under inversion at In 0.53 Ga 0.47 As/Al 2 O 3 interfaces. Through density-functional calculations, these defects are found to be thermodynamically stable in amorphous Al 2 O 3 and to be able to capture two electrons in a dangling bond upon breaking bonds with neighboring O atoms. Through a band alignment based on hybrid functional calculations, it is inferred that the corresponding defect levels lie at ∼1 eV above the conduction band minimum of In 0.53 Ga 0.47 As, in agreement with measured defect densities. These results support the technological importance of avoiding cation diffusion into the oxide layer.The microelectronic industry is investigating high mobility semiconductors for replacing silicon as substrate material. Among the III-V compounds, the In x Ga 1−x As family has gathered large interest for application in n-type devices.1 In particular, the compound In 0.53 Ga 0.47 As (here referred to as InGaAs) has suitable electronic properties for microelectronic devices and can easily be grown onto InP substrates.1,2 Amorphous Al 2 O 3 is the preferred dielectric owing to its wide bandgap, high breakdown field, and high thermal stability. 2Several passivation procedures have been considered to reduce the high density of interfacial defect states occurring at III-V/oxide interfaces (D it ).3-7 The origin of these states has been for long debated and recently assigned to As-As dimer bonds. [8][9][10][11][12][13] In addition to these interfacial states, a high density of oxide traps (D ot ) has recently been detected in the oxide layer of metal-oxide-semiconductor (MOS) devices. Capacitancevoltage (CV) measurements show a bimodal distribution for the density of defect states in the oxide, 14 with one peak at 1.5 eV above and the other at 0.5 eV below the CBM of InGaAs. Similarly, through positive bias temperature instability (PBTI) experiments, a wide distribution of defect states centered at about 1 eV above the InGaAs conduction band maximum (CBM) has been inferred.15 These states are considered to be at the origin of the degradation of the electrical properties, thereby compromising the performance of the corresponding MOS devices.14,15 Indeed, upon reaching the inversion of carrier population, the Fermi energy is pushed deep into the conduction band of InGaAs in order to achieve high carrier concentrations, and is then susceptible to defects in the upper part of the oxide band gap. The atomic origin of these defects has remained elusive. A hint might come from electrical measurements on InGaAs/Al 2 O 3 and Ge/GeO x /Al 2 O 3 interfaces which yield similar field acceleration factors, 16 but an assessment concerning the nature of the involved defects remains out of reach on this basis. More indicatively, a) Electronic mail: davide.colleoni@epfl.ch time-of-flight secondary ion mass spectroscopy studies on GaAs/Al 2 O 3 and InGaAs/Al 2 O 3 interfaces revea...

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“…Computations in the framework of numerical models indicated that arsenic defect complexes, such as As-As dimer/dangling bond, are good candidates for amphoteric mid-gap defect levels. Such models also describe the abrupt interfaces of GaAs/Al 2 O 3 quite well [43]. Apparently, the real structure of the natural oxide layer in III-As compounds is quite complex.…”

Section: Resultsmentioning

confidence: 96%

Unified mechanism of the surface Fermi level pinning in III-As nanowires

et al. 2018

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Fermi level pinning at the oxidized (110) surfaces of III-As nanowires (GaAs, InAs, InGaAs, AlGaAs) is studied. Using scanning gradient Kelvin probe microscopy, we show that the Fermi level at oxidized cleavage surfaces of ternary Al Ga As (0 ≤ x ≤ 0.45) and Ga In As (0 ≤ x ≤ 1) alloys is pinned at the same position of 4.8 ± 0.1 eV with regard to the vacuum level. The finding implies a unified mechanism of the Fermi level pinning for such surfaces. Further investigation, performed by Raman scattering and photoluminescence spectroscopy, shows that photooxidation of the Al Ga As and Ga In As nanowires leads to the accumulation of an excess of arsenic on their crystal surfaces which is accompanied by a strong decrease of the band-edge photoluminescence intensity. We conclude that the surface excess arsenic in crystalline or amorphous forms is responsible for the Fermi level pinning at oxidized (110) surfaces of III-As nanowires.

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Defect state passivation at III-V oxide interfaces for complementary metal–oxide–semiconductor devices

Cited by 86 publications

References 85 publications

Electrical properties of GaAs metal–oxide–semiconductor structure comprising Al2O3 gate oxide and AlN passivation layer fabricated in situ using a metal–organic vapor deposition/atomic layer deposition hybrid system

Electrical properties of GaAs metal–oxide–semiconductor structure comprising Al2O3 gate oxide and AlN passivation layer fabricated in situ using a metal–organic vapor deposition/atomic layer deposition hybrid system

Nature of electron trap states under inversion at In0.53Ga0.47As/Al2O3 interfaces

Unified mechanism of the surface Fermi level pinning in III-As nanowires

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