Defect size variations and their effect on the critical area of VLSI devices

Ferris-Prabhu, A.V.

doi:10.1109/jssc.1985.1052404

Cited by 72 publications

(18 citation statements)

References 2 publications

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“…A(r) is referred to as the critical area for defect size r. The total critical area integral A c for all defect sizes is also referred to as the weighted critical area. The defect density function has been estimated as follows [73,27,66]:…”

Section: A(r)d(r)drmentioning

confidence: 99%

Yield Analysis and Optimization

Gupta¹,

Papadopoulou²

2008

Handbook of Algorithms for Physical Design Automation

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In this chapter, we are going to discuss yield loss mechanisms, yield analysis and common physical design methods to improve yield. Yield is defined as the ratio of the number of products that can be sold to the number of products that can be manufactured. Estimated typical cost of modern 300mm or 12inch wafer 0.13 µm process fabrication plant is $2-4 billion. Typical number of processing steps for a modern integrated circuit is more than 150.Typical production cycle-time is over 6 weeks. Individual wafers cost multiple thousands of dollars. Given such huge investments, consistent high yield is necessary for faster time to profit.

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Section: A(r)d(r)drmentioning

confidence: 99%

Yield Analysis and Optimization

Gupta¹,

Papadopoulou²

2008

Handbook of Algorithms for Physical Design Automation

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“…The evaluation of the effects of manufacturing defects on an IC is related to the defect density (given by D), the extent by which defects are clustered (parameterized by α), and the critical area (denoted as A) exposed to the defects [26], [27]. The expected average number of faults on a chip is given by λ 0 = AD.…”

Section: Global Yield Modelmentioning

confidence: 99%

“…The feature of a critical area is related to the presence of a defect as a possibly fatal event (i.e., a fault); hence, the size of the circuit pattern in a chip is used to establish whether a defect can cause a fault. In [26] and [27], they have been analyzed through a function fault probability kernel K(x), which is zero when a defect does not cause a fault and one otherwise. The critical area of a circuit is, then, the product of the actual area and the integral of the product of the defect size distribution and the kernel function [26], [27].…”

Section: Global Yield Modelmentioning

confidence: 99%

Evaluating the Yield of Repairable SRAMs for ATE

Ottavi

Schiano

Wang

et al. 2006

IEEE Trans. Instrum. Meas.

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Abstract-An accurate yield evaluation is essential in selecting redundancy allocation and testing strategies for memories. Yield evaluation can resolve the many issues revolving around costeffective built-in self-test (BIST) and automatic test equipment (ATE)-based solutions for a higher test transparency. In this paper, two yield-calculation methodologies for SRAM arrays are proposed. General yield expressions for VLSI chips are initially presented. The regular and repetitive structure of an SRAM array is exploited, and substantial yield improvements can be achieved by the introduction of redundancy. Two repair yield-evaluation methods for one-dimensional redundant memory arrays are introduced and compared for ATE application. The first method is based on the sum of the probabilities of all repairable fault patterns; the second method is based on Markov modeling. Using industrial data, it is shown that these methods are applicable to ATE usage under different conditions of defect rate in the possible defects. Different features of the proposed methods are discussed.

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“…To this extent, the concept of defect-sensitivity is introduced, and several analytical defect size distributions are studied in conjunction with analytical yield formulae [8], [9]. As a result, a "design oriented" yield prediction methodology is developed which takes into account the layout, the process, and the environmental conditions of the manufacturing line.…”

Section: Layout Defect-sensitivity Analysismentioning

confidence: 99%

Course development in IC manufacturing

Gyvez

1994

IEEE Trans. Educ.

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Abstract-Traditional curriculum in electrical engineering separates semiconductor processing courses from courses in circuit design. As a result, manufacturing topics involving yield management, and the study of random process variations impacting circuit behavior are usually vaguely treated. The subject matter of this paper is to report a course developed at Texas A&M University to compensate for the aforementioned shortcoming. This course attempts to link technological process and circuit design domains by emphasizing aspects such as process disturbance modeling, yield modeling, and defect-induced fault modeling. In a rapidly changing environment where high-end technologies are evolving towards submicron features and towards high transistor integration, these aspects are key factors to design for manufucturubility. The paper presents the course's syllabus, a description of its main topics, and results on selected project assignments carried out during a normal academic semester.

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Defect size variations and their effect on the critical area of VLSI devices

Cited by 72 publications

References 2 publications

Yield Analysis and Optimization

Yield Analysis and Optimization

Evaluating the Yield of Repairable SRAMs for ATE

Course development in IC manufacturing

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