Defect profiling in FEFET Si:HfO2 layers

O’Sullivan, Barry; Putcha, Vamsi; Izmailov, R. A.; Afanasʼev, Valeri; Simoen, Eddy; Jung, Tae Sik; Higashi, Y.; Degraeve, R.; Truijen, Brecht; Kaczer, B.; Ronchi, Nicolò; McMitchell, S. R. C.; Banerjee, K.; Clima, Sergiu; Breuil, L.; bosch, G. Van den; Linten, Dimitri; Houdt, J. Van

doi:10.1063/5.0029072

Cited by 23 publications

(3 citation statements)

References 11 publications

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“…This technique is called as the measure-stress-measure (MSM). [22][23][24][25] In this technique, initially the I-V characteristics of the fresh device is measured, then the stress is applied at high temperature for some time interval, for example, 2000s. This process is repeated several times to measure the degradation due to BTI stress.…”

Section: Simulation Parameters and Device Structurementioning

confidence: 99%

“…The device transfer curve are evaluated before and after BTI stress for determining the variation in the parameters. This technique is called as the measure‐stress‐measure (MSM) 22–25 . In this technique, initially the I–V characteristics of the fresh device is measured, then the stress is applied at high temperature for some time interval, for example, 2000s.…”

Section: Simulation Parameters and Device Structurementioning

confidence: 99%

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Assessment of BTI‐induced deterioration in vacuum based undoped structure

Kumar,

Panchore

2024

Int J Numerical Modelling

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In this paper, an assessment of bias temperature instability (BTI) in based dual gate dopingless JLFET (HKV‐DLJLFET) is carried out at 15 nm technology node. For this, the gate dielectric of HKV‐DGDLJLFET is made of asymmetric combination of and vacuum dielectrics near the source/drain (S/D) side, which significantly minimizes the leakage current and enhances the reliability. Our simulation study have shown that the n‐type HKV‐DGDLJLFET exhibits 2.28 and 2.45 times less deterioration in drain current and transconductance respectively, than n‐type HKV‐DGJLFET due to positive BTI (PBTI) for 2000 seconds at . Further, we have found that n‐type HKV‐DGDLJLFET has less deterioration in and due to BTI stress for different time spans. Hence, adding vacuum dielectric to the drain side lowers the BTI stress at high temperatures and makes it last longer.

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Section: Simulation Parameters and Device Structurementioning

confidence: 99%

Section: Simulation Parameters and Device Structurementioning

confidence: 99%

Assessment of BTI‐induced deterioration in vacuum based undoped structure

Kumar,

Panchore

2024

Int J Numerical Modelling

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“…coercive voltage) [18]. Furthermore, the effect of polarization on threshold voltage was turned out through the comparison experiment of the characteristics of HK-FET (PE-FET) versus FE-FET [19]. In this work, as a follow-up research, the dependence of threshold voltage on both Si doping concentration and the biasing voltage at room/high temperatures is investigated with experiment data, and then, the competition between polarization switching and charge trapping is discussed.…”

Section: Introductionmentioning

confidence: 99%

Experimental study of threshold voltage shift for Si:HfO₂ based ferroelectric field effect transistor

Jung¹,

Shin²

2021

Nanotechnology

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For a given three different Si doping concentrations at room and high temperatures, the threshold voltage shift (ΔV th ) on silicon-doped hafnium-oxide-based ferroelectric field effect transistor (FeFET) is experimentally investigated. It turned out that charge trapping in the gate stack of FeFET (versus polarization switching in the gate stack of FeFET) adversely affects ΔV th . Charge trapping causes the positive ΔV th , while polarization switching causes the negative ΔV th . The dominance of polarization switching is predominantly determined by the total remnant polarization (2P r ), which can be controlled by adjusting Si doping concentration in the hafnium-oxide layer. As the Si doping concentration increases from 2.5% to 3.6%, and 5.0%, 2P r decreases 19.8 μC cm −2 to 15.25 μC cm −2 , and 12.5 μC cm −2 , which leads to ΔV th of −0.8 V, −0.09 V, and +0.1 V, respectively, at room temperature. At high temperature, the effect of polarization switching is degraded due to the decreased P r , while the effect of charge trapping is very independent of temperature. For those three different Si doping concentrations (i.e. 2.5%, 3.6%, and 5.0%), at the high temperature, ΔV th of FeFET is −0.675 V, −0.075 V, and +0.15 V, respectively. This experimental work should provide an insight for designing FeFET for memory and logic applications.

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On the strong coupling of polarization and charge trapping in HfO2/Si-based ferroelectric field-effect transistors: overview of device operation and reliability

2022

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Defect profiling in FEFET Si:HfO2 layers

Cited by 23 publications

References 11 publications

Assessment of BTI‐induced deterioration in vacuum based undoped structure

Assessment of BTI‐induced deterioration in vacuum based undoped structure

Experimental study of threshold voltage shift for Si:HfO₂ based ferroelectric field effect transistor

On the strong coupling of polarization and charge trapping in HfO2/Si-based ferroelectric field-effect transistors: overview of device operation and reliability

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Defect profiling in FEFET Si:HfO2 layers

Cited by 23 publications

References 11 publications

Assessment of BTI‐induced deterioration in vacuum based undoped structure

Assessment of BTI‐induced deterioration in vacuum based undoped structure

Experimental study of threshold voltage shift for Si:HfO2 based ferroelectric field effect transistor

On the strong coupling of polarization and charge trapping in HfO2/Si-based ferroelectric field-effect transistors: overview of device operation and reliability

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Experimental study of threshold voltage shift for Si:HfO₂ based ferroelectric field effect transistor