Defect Passivation With Fluorine and Interface Engineering for Hf-Based High- &lt;formula formulatype="inline"&gt;&lt;tex&gt;$k$&lt;/tex&gt;&lt;/formula&gt;/Metal Gate Stack Device Reliability and Performance Enhancement

Tseng, Hsing‐Huang; Tobin, P.J.; Kalpat, S.; Schaeffer, J.; Ramon, M.; Fonseca, L. R. C.; Jiang, Z.X.; Hegde, Rama I.; Triyoso, Dina H.; Semavedam, S.

doi:10.1109/ted.2007.908897

Cited by 54 publications

(37 citation statements)

References 18 publications

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“…Fluorinated devices exceed the V t TTF lifetime target (<30 mV Vt shift in 10 years at 105°C for V dd = 1 V) with a sufficient margin and reveal about a four orders of magnitude longer PBTI lifetime than the control that does not incorporate fluorine. SIMS analysis results confirmed the incorporation of fluorine at the interfaces and bulk high-k [35], which is expected to reduce the defect density and thus reduce charge trapping. It has been shown that oxygen vacancies are the major defects in the bulk HfO 2 [36].…”

Section: Fluorine Passivation Coupled With Srpo [35]mentioning

confidence: 65%

“…Incorporating fluorine into the bulk HfO 2 and interfaces can passivate the defects, thus improving the device robustness and speed. Combining SRPO interface engineering and defect passivation with fluorine in a high-k/Ta x C y stack showed excellent V t stability [35]. The positive bias temperature instability (PBTI) time to failure (TTF)-lifetime extraction using stress voltages in the direct tunneling regime is shown in Fig.…”

Section: Fluorine Passivation Coupled With Srpo [35]mentioning

confidence: 98%

“…There is a concern that the mobility of the channel carriers may be degraded by interactions with these soft phonons. [8][9][10][11][12][13][14][15][16][17][18] These metal oxides have reasonably high dielectric constants and band gaps (see Figure 3). Both ZrO 2 and HfO 2 devices have demonstrated a many orders of magnitude reduction in gate leakage with an EOT around 1.0 nm and well-behaved t r a n s i s t o r s .…”

Section: Oxygen Diffusion Through the Grain Boundary Of Metal Oxidementioning

confidence: 99%

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The Progress and Challenges of Applying High-k/Metal-Gated Devices to Advanced CMOS Technologies

Tseng¹

2010

Solid State Circuits Technologies

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Introduction Motivation for implementing high dielectric constant gate dielectric for advanced CMOS scalingSemiconductor devices need to have good performance, with a low cost and low power dissipation. For decades, research and development of semiconductor processing technology and device integration have focused on enhancing performance and reducing costs using SiO 2 as the gate dielectric and doped polysilicon as the gate electrode. The most effective way to enhance performance and reduce costs is to scale the device gate length and gate oxide. Scaling the gate length results in fabricating more devices per wafer (i.e., increase the device density) and thus reduce the cost per chip, while scaling the gate oxide enhances the drive current and reduces the short channel effects due to gate length scaling. However, as the gate oxide becomes thinner, the power to operate transistors increases because of greater gate oxide leakage current. To resolve this high gate oxide leakage problem, the mechanism of the carriers tunneling through the gate dielectric must be better understood. In an ideal metal-insulator-semiconductor (MIS) device, the current conduction in the insulator should be zero. In a real MIS device, however, current can flow through the insulating film by various conduction mechanisms. The two primary conduction mechanisms for electron tunneling through high quality gate dielectric are discussed below. Direct tunnelingIn a metal-insulator-semiconductor (MIS) stack, when the oxide voltage (V ox ) is smaller than the metal-insulator barrier height, the electron tunnels directly from the metal electrode into other semiconductor electrode through the insulator. This is known as the direct tunneling process. The equation for direct tunneling current density (current normalized by device area) is proportional to

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Section: Fluorine Passivation Coupled With Srpo [35]mentioning

confidence: 65%

Section: Fluorine Passivation Coupled With Srpo [35]mentioning

confidence: 98%

Section: Oxygen Diffusion Through the Grain Boundary Of Metal Oxidementioning

confidence: 99%

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The Progress and Challenges of Applying High-k/Metal-Gated Devices to Advanced CMOS Technologies

Tseng¹

2010

Solid State Circuits Technologies

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“…To improve tunnel oxide reliability, a fluorine incorporation technique was reported [44][45][46]. Incorporating fluorine in the tunnel dielectric improves the Si/SiO 2 interface, resulting in excellent endurance over a 3 V P/E window for at least 1E + 05 cycles because the fluorine passivates defects in the tunnel oxide stack.…”

Section: Tunnel Barrier Engineering (Tbe)mentioning

confidence: 99%

Barrier engineering in metal–aluminum oxide–nitride–oxide–silicon (MANOS) flash memory: Invited

Kang¹

2010

Current Applied Physics

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“…For the commonly used polycide process, fluorine is inadvertently introduced into the gate oxide from WSix deposition using WF 6 gas. The effects of fluorine have been studied intensively such as reliability issues [1][2][3], device performance [4,5], and the physical properties of gate oxide [6]. However, few studies have focused on the fluorine effect as the function of the channel length.…”

Section: Introductionmentioning

confidence: 99%

Fluorine Effects on NMOS Characteristics and DRAM Refresh

Choi¹

2012

JSTS:Journal of Semiconductor Technology and Science

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Abstract-We observed that in chemical vapor deposition (CVD) tungsten silicide (WSix) poly gate scheme, the gate oxide thickness decreases as gate length is reduced, and it intensifies the roll-off properties of transistor. This is because the fluorine diffuses laterally from WSix to the gate sidewall oxide in addition to its vertical diffusion to the gate oxide during gate re-oxidation process. When the channel length is very small, the gate oxide thickness is further reduced due to a relative increase of the lateral diffusion than the vertical diffusion. In DRAM cells where the channel length is extremely small, we found the thinned gate oxide is a main cause of poor retention time.

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Defect Passivation With Fluorine and Interface Engineering for Hf-Based High- <formula formulatype="inline"><tex>$k$</tex></formula>/Metal Gate Stack Device Reliability and Performance Enhancement

Cited by 54 publications

References 18 publications

The Progress and Challenges of Applying High-k/Metal-Gated Devices to Advanced CMOS Technologies

The Progress and Challenges of Applying High-k/Metal-Gated Devices to Advanced CMOS Technologies

Barrier engineering in metal–aluminum oxide–nitride–oxide–silicon (MANOS) flash memory: Invited

Fluorine Effects on NMOS Characteristics and DRAM Refresh

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