Defect Modeling Using Fault Tuples

Blanton, R. D.; Dwarakanath, K.N.; Desineni, R.

doi:10.1109/tcad.2006.870836

Cited by 34 publications

(11 citation statements)

References 44 publications

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“…At the layout level, nets that are physically close to the defect site (i.e., neighbors) that are found to influence defect activation are identified. The neighbors and the logic values required for defect activation are mapped to a set of one or more fault-tuple products [124], which are then disjunctively combined into a macrofault which is an expression that represents the logical conditions that must be satisfied for a site to become faulty. For example, the macrofault (n 1 ,0,i) c (n 2 ,0,i) c (s x ,1,i) e + (n 1 ,1,i) c (n 2 ,1,i) c (s x ,1,i) e indicates that site s x becomes stuck-at-1 when n 1 =n 2 =0 or n 1 =n 2 =1.…”

Section: Methodology Evaluationmentioning

confidence: 99%

“…For example, the macrofault (n 1 ,0,i) c (n 2 ,0,i) c (s x ,1,i) e + (n 1 ,1,i) c (n 2 ,1,i) c (s x ,1,i) e indicates that site s x becomes stuck-at-1 when n 1 =n 2 =0 or n 1 =n 2 =1. (More details of fault-tuple macrofaults can be found in [124].) The resulting macrofault is then fault simulated using all test patterns applied to the failing chip.…”

Section: Methodology Evaluationmentioning

confidence: 99%

“…While it is true that many defect behaviors can be mapped to the logic-level [124] to gain scalability, the mapping process often requires pre-characterization of the defect behaviors [121]. In addition, logic-level abstraction will not be able to capture/simulate defect behavior that is both a function of the tests applied and its physical location of occurrence.…”

Section: Our Contributionmentioning

confidence: 99%

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Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Tam¹,

Blanton

2012

IEEE Des. Test. Comput.

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In the integrated circuit (IC) industry, all products must go through three phases before they are available in the market, namely design, manufacturing, and testing. Design, obviously, refers to the process of converting the early concepts of the product into a precise description of its implementation. Manufacturing then uses this description to fabricate the product, where the design is physically materialized onto the silicon wafer and later packaged into the product. If design and manufacturing are perfect, then every fabricated IC is completely functional, thereby obliterating the need for testing. Unfortunately, both design and manufacturing are not ideal; therefore every manufactured IC must be subject to stringent testing procedures to ensure that most bad ICs are identified and prevented from shipping to the end-users.ICs are deemed bad when they contain certain defects that cause the ICs to fail the specifications.Defects are unintended structural and/or material changes of the IC due to design/manufacturing imperfections.These physical changes may alter the electrical characteristics of the circuit, which are sometimes severe enough to lead to a failure (i.e., violation of one or more design specifications). Common defects in IC manufacturing can be caused by contaminations in the process, variations of the process conditions, or simply the difficulty to fabricate certain features of the design. The last issue is the focus of this dissertation. Defects that arise due to certain aspects of the design being sensitive to the manufacturing process with an elevated likelihood of failure are known as systematic defects. This dissertation addresses the issues related to the prevention and identification of systematic defects by analyzing a large amount of manufactured ICs that have failed testing.For systematic-defect prevention, one common approach is to use design-for-manufacturability (DFM) rules to communicate hard-to-manufacture features to designers so that these features can be minimized in the iii design. Obviously, different rules describe different features and thus their violation/adherence will have different impact on the manufacturability of the product. It is therefore desirable to measure the relative importance of the rules and how they affect product yield. To address this issue, a method called RADAR (Rule Assessment of Defect-Affected Regions) has been developed for measuring the effectiveness of DFM rules in preventing systematic defects. RADAR analyzes a large amount of test data of failed ICs to draw statistical conclusion.Taking preventive measures, such as enforcing DFM rules, is necessary to ensure sufficient product yield. Unfortunately, the amount of resource (circuit area, designer's time, etc.) dedicated to DFM can be quite limited. It is therefore impractical to anticipate and prevent every possible hard-to-manufacture design features before the product is manufactured. Thus, systematic defects can still exist. Therefore, a mechanism is required to identify systematic ...

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Section: Methodology Evaluationmentioning

confidence: 99%

Section: Methodology Evaluationmentioning

confidence: 99%

Section: Our Contributionmentioning

confidence: 99%

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Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Tam¹,

Blanton

2012

IEEE Des. Test. Comput.

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“…This is possible because the underlying debug algorithm is a modelfree one that works with both errors and faults [20]. It is also because most physical defects can be modeled in terms of design errors as extensively discussed in [27], [28].…”

Section: Application To Physical Defectsmentioning

confidence: 99%

Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment

Yang

Veneris

Nicolici

2012

IEEE Trans. VLSI Syst.

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Abstract-With the growing size of modern designs and more strict time-to-market constraints, design errors can unavoidably escape pre-silicon verification and reside in silicon prototypes. Due to those errors and faults in the fabrication process, silicon debug has become a necessary step in the digital integrated circuit design flow. Embedded hardware blocks, such as scan chains and trace buffers, provide a means to acquire data of internal signals in real time for debugging. However, the amount of the data is limited compared to pre-silicon debugging. This paper presents an automated software solution to analyze this sparse data to detect suspects of the failure in both the spatial and temporal domain. It also introduces a technique to automate the configuration process for trace-buffer based hardware in order to acquire helpful information for debugging the failure. The technique takes the hardware constraints into account and identifies alternatives for signals not part of the traceable set so that their values can be restored by implications. The experiments demonstrate the effectiveness of the proposed software solution in terms of run-time and resolution.

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“…To our knowledge, [16] and [17] are the only two papers that discuss how to distinguish different types of faults so far. In [16], a diagnostic test generation technique for arbitrary faults is proposed which uses a defect modeling technique called fault tuples [18] to model various fault types. A Boolean Satisfiability formulation is developed which helps generate diagnosis patterns for two fault-injected circuits.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Diagnosis Pattern Generation Procedure to Distinguish Stuck-at Faults and Bridging Faults

Lee

2014

2014 IEEE 23rd Asian Test Symposium

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Fault Diagnosis is a critical process to identify the locations of physical defects in advanced integrated circuits. Current diagnosis tools often report multiple types of faults as defect candidates. Thus an efficient method to distinguish different types of faults is highly desired. Stuck-at and bridging faults are two most commonly used DC fault models during diagnosis. In this paper we present an efficient diagnosis pattern generation procedure to distinguish stuck-at faults and bridging faults. Two major techniques are proposed. The first one is a fault-inactivation methodFIM) that can quickly distinguish most fault pairs by inactivating one fault while detecting the other in each fault pair. The second one is a fault-types-transformation method (FTTM) that can transform the problem of distinguishing a stuck-at fault and a bridging fault into the problem of detecting a stuck-at fault. Both methods involve only one copy of the original circuit and require only an ordinary ATPG tool for stuck-at faults. Furthermore, both methods can deal with multiple fault pairs at a time and thus not only is the required CPU time small but also the dynamic test compaction capability of the ATPG tool can be utilized. Experiments on a large number of randomly selected fault pairs in ISCAS'89 and IWLS'05 benchmark circuits have been carried out. The results show that the FIM can distinguish about 91.9% of distinguishable fault pairs quickly and the FTTM can distinguish all other distinguishable fault pairs and identify all equivalent fault pairs. The average ratio of the number of diagnosis patterns over that of the test patterns for stuck-at faults is only 0.64. On average, one diagnosis pattern can distinguish 10.89 fault pairs.

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Defect Modeling Using Fault Tuples

Cited by 34 publications

References 44 publications

Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment

An Efficient Diagnosis Pattern Generation Procedure to Distinguish Stuck-at Faults and Bridging Faults

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