Defect evaluation in InGaAs field effect transistors with HfO2 or Al2O3 dielectric

Abstract

Articles you may be interested inImpact of Fermi level pinning inside conduction band on electron mobility in InGaAs metal-oxide-semiconductor field-effect transistors HfO2 dielectrics engineering using low power SF6 plasma on InP and In0.53Ga0.47As metal-oxidesemiconductor field-effect-transistors Appl.

An Amorphous Silicon Photo TFT with Si3N4/Al2O3 or HfO2 Double Layered Insulator for Digital Imaging Applications

“…6b) the on-current under illumination is higher for HfO2 in APT3 than for APT2. The same findings were reported in [17] and in [19] where it was shown that the Al2O3 transistors show the best subthreshold slope and the interface trap density and that the HfO2 transistors reach a higher transconductance. 3.41×10 -6 3.66×10 -9 1.39×10 -8 t (Si3N4/Al2O3)= 30 nm/1 nm 0.93 0.93 9.94×10 -7 3.39×10 -6 3.44×10 -9 1.31×10 -8 t (Si3N4 /HfO2) = 30 nm/1 nm 0.9 0.9 9.98×10 -7 3.40×10 -6 3.57×10 -9 1.35×10 -8 t (Si3N4) = 30 nm 0.89 0.88 1.00×10 -6 3.41×10 -6 3.66×10 -9 1.39×10 -8 t(Si3N4 /Al2O3) = 30 nm/30 nm 1.9 1.89 8.18×10 -7 2.79×10 -6 1.07×10 -9 4.61×10 -9 t (Si3N4 /HfO2) = 30 nm/30 nm 1.3 1.3 9.25×10 -7 3.15×10 -6 1.91×10 -9 7.67×10 -9 t(Si3N4) = 30 nm 0.89 0.88 1.00×10 -6 3.41×10 -6 3.66×10 -9 1.39×10 -8 t (Si3N4 /Al2O3) = 30 nm/150 nm 4.57 4.55 2.70×10 -7 9.46×10 -7 1.77×10 -10 1.30×10 -9 t (Si3N4 /HfO2) = 30 nm/150 nm 3.02 3.01 6.01×10 -7 2.05×10 -6 5.26×10 -10 2.62×10 -9…”

“…Since several years and for many applications, many structures for transistors and phototransistors were investigated in order to improve device performance [7]- [14]. Among these structures, were reported transistors with dual layer gate dielectric [15], [16], and/or high k materials as gate dielectrics [17]- [19]. It has been demonstrated that dual-layer dielectric structures are used because of two major advantages: high yield and improved transistors characteristics [20].…”

Low-frequency noise in nanowire and planar III-V MOSFETs

“…A schematic of the planar device structure is provided in Fig. 1(d) and details about the processing can be found in [15]. Fig.…”

Extensive assessment of the charge-trapping kinetics in InGaAs MOS gate-stacks for the demonstration of improved BTI reliability

“…O enable future high-speed and low-power logic technologies, MOSFETs with high mobility channel materials are being explored as they provide higher drive current for scaled dimensions [1][2][3][4]. InGaAs has a lower bandgap (0.72 eV) than Si, and higher electron mobility, thus making it a suitable candidate for channel material for future low-power MOS devices.…”