Defect Engineering and Stress Control in Advanced Devices on High-Mobility Substrates

Claeys, Cor; Eneman, G.; Simoen, Eddy

doi:10.1109/icmel.2006.1650898

Cited by 2 publications

(2 citation statements)

References 52 publications

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“…It has recently been shown that there exists a clear correlation between the TD density and the electrical performance of SiGe structures such as junction leakage current and carrier lifetime. 4,5 Recessed SiGe S/D structures in combination with a high-gate dielectric also lead to a higher low-frequency noise level. 6,7 For advanced p-channel metal oxide semiconductor field effect transistors ͑pMOSFETs͒, a suitable technique to enhance the hole channel mobility is by replacing the silicon source/drain ͑S/D͒ regions by SiGe ones.…”

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confidence: 99%

Leakage Current Control in Recessed SiGe Source/Drain Junctions

Claeys

González

Eneman

et al. 2007

J. Electrochem. Soc.

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The impact of different process parameters, namely, the trench etch depth, the total epitaxial SiGe thickness, and the epi elevation, on the leakage current of recessed Si 0.8 Ge 0.2 source/drain junctions has been systematically investigated. Besides the behavior of the forward and the reverse currents, attention is also given to the temperature dependence of the leakage current. It is found that both the bulk and the peripheral leakage current density increase strongly with increasing etch depth. Empirically, an exponential dependence has been observed between the area leakage current density at Ϫ1 V and the distance d j between the Si 0.8 Ge 0.2 -Si interface and the electrical p-n junction, whereby an increase by 1 dec for every 43 nm of reduction in d j occurs. This can be understood by the fact that the responsible defects originate mainly at the SiGe-Si interface. The perimeter current density shows for certain process splits an exponential dependence on the total thickness of the epitaxial layer t SiGe , with an increase by a decade for every 50 nm increase in thickness. Also, the generation and recombination lifetimes have been studied in order to determine an effective energy level of the electrically active defects.

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confidence: 99%

Leakage Current Control in Recessed SiGe Source/Drain Junctions

Claeys

González

Eneman

et al. 2007

J. Electrochem. Soc.

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“…As will be illustrated, TDs can enhance the diode leakage current, degrade the carrier lifetime and increase the low frequency noise. Reviews on defect engineering and stress control in advanced devices on high-mobility substrates have been published by the authors (6,7).…”

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confidence: 99%

Electrical Performance and Reliability Aspects of Strain Engineered Deep Submicron CMOS Technologies

Claeys¹,

Eneman²,

González³

et al. 2007

ECS Trans.

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To keep track with Moore's law, strain engineering based on either a global or a local approach is gaining much interest and has already been successfully implemented for 65 and 45 nm technology nodes. Although the first goal is to improve the drive current by mobility enhancement, other performance parameters such as leakage current, carrier lifetime and low frequency 1/f noise have to be considered. The implementation of stressors also impacts the radiation hardness of the devices. First some general comments are given on strain engineering techniques already used, before discussing more in detail their impact on several electrical device parameters. Attention mainly will be given to illustrate a global approach based on strained Si on strain-relaxed SiGe buffer layers and the use of process-induced stressors such as an embedded SiGe layer and a contact etch stop layer (CESL). Both are gaining strong interest for implementation in a FinFET technology. Some advantages and disadvantages of the different approaches will be outlined.

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Defect Engineering and Stress Control in Advanced Devices on High-Mobility Substrates

Cited by 2 publications

References 52 publications

Leakage Current Control in Recessed SiGe Source/Drain Junctions

Leakage Current Control in Recessed SiGe Source/Drain Junctions

Electrical Performance and Reliability Aspects of Strain Engineered Deep Submicron CMOS Technologies

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