Deep submicron CMOS technology enables system-on-chip for wireless communications ICs

Hammes, M.; Kranz, C.; Seippel, D.

doi:10.1109/mcom.2008.4623721

Cited by 6 publications

(3 citation statements)

References 11 publications

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“…where = /( ox V sat ) and od is the gate overdrive voltage given in (2). The revised total channel charge can be obtained by integrating the drain current from 0 to elec with the expression of ( ) in (15).…”

Section: Modeling Thermal Noise In Short-channel Devicesmentioning

confidence: 99%

“…While bipolar technologies have traditionally dominated RF designs due to their superior switching frequency and gain, they are not particularly suited for low power design and are not directly compatible with scaled digital CMOS processes. In the late 1990s, the transit frequency of CMOS devices reached the 40 GHz range, which enabled the design and implementation of RF CMOS circuits that could process signals on the order of 4 GHz [2]. A combination of improved processing technology, suitable MOS circuit architectures, and amenable wireless standards have helped push CMOS technology to the forefront for RF circuit implementations [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

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The Design of Low Noise Amplifiers in Deep Submicron CMOS Processes: A Convex Optimization Approach

Hoe

Jin

2015

VLSI Design

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With continued process scaling, CMOS has become a viable technology for the design of high-performance low noise amplifiers (LNAs) in the radio frequency (RF) regime. This paper describes the design of RF LNAs using a geometric programming (GP) optimization method. An important challenge for RF LNAs designed at nanometer scale geometries is the excess thermal noise observed in the MOSFETs. An extensive survey of analytical models and experimental results reported in the literature is carried out to quantify the issue of excessive thermal noise for short-channel MOSFETs. Short channel effects such as channel-length modulation and velocity saturation effects are also accounted for in our optimization process. The GP approach is able to efficiently calculate the globally optimum solution. The approximations required to setup the equations and constraints to allow convex optimization are detailed. The method is applied to the design of inductive source degenerated common source amplifiers at the 90 nm and 180 nm technology nodes. The optimization results are validated through comparison with numerical simulations using Agilent’s Advanced Design Systems (ADS) software.

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Section: Modeling Thermal Noise In Short-channel Devicesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

The Design of Low Noise Amplifiers in Deep Submicron CMOS Processes: A Convex Optimization Approach

Hoe

Jin

2015

VLSI Design

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“…due to their extremely small feature size [1]. Smaller feature sizes are being aggressively pursued to meet the demand for faster circuitry and higher levels of integration, but this presents increasing challenges for RF designers.…”

mentioning

confidence: 99%

Lumped-Element Wilkinson Power Combiners Using Reactively Compensated Star/Delta Coupled Coils in 28-nm Bulk CMOS

Love

Thian

Wilt³

et al. 2019

IEEE Trans. Microwave Theory Techn.

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This paper presents four compact lumped-element Wilkinson power combiners (WPC) operating at 5 GHz in 28-nm bulk CMOS. To minimize the chip area, the inductances in the designs are implemented using mutually coupled coils. Two designs use star inverting coupled coils (SICC), while the other two employ delta noninverting coupled coils (DNICC). One of the two SICC-based designs (and similarly for the DNICC-based designs) incorporates a second harmonic (2f 0 ) trap to lower the total harmonic distortion and reduce the required inductances by 25%, further reducing the circuits footprint. A design methodology for effectively exploiting the mutual coupling and nullifying the coupling parasitics is presented. The coupling parasitic in the DNICC-based design is exploited to provide the WPC isolation resistance, resulting in a lumped-element WPC requiring only three components: a coupled coil and two capacitors. The measurement and simulation results are presented to confirm the theory validity. The SICC-based WPC with an area of 0.13 mm 2 achieved input return losses (RL) >17.5 dB, output RL > 11.8 dB, isolation >11.2 dB, and insertion losses (IL) <1.5 dB across 3.5-5.4-GHz frequency range. Its variant with a 2f 0 trap achieved, from 3.5-5.35 GHz, input RL >18.2 dB, output RL >11.6 dB, isolation >11 dB, IL <1.4 dB, and peak 2f 0 rejection of 18 dB at 10.2 GHz in an area of 0.13 mm 2 .The DNICC-based WPC with an area of 0.11 mm 2 achieved input RL and isolation >10 dB, output RL >15.3 dB, and IL <1.2 dB across 4.1-5.45-GHz frequency range. Its variant with a 2f 0 trap achieved, from 4.3-5.3 GHz, input RL and isolation >10.1 dB, output RL >14.6, IL <1.2 dB, and peak 2f 0 rejection of 23 dB at 10.4 GHz in an area of 0.09 mm 2 .

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2011

Digital Design of Signal Processing Systems

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Deep submicron CMOS technology enables system-on-chip for wireless communications ICs

Cited by 6 publications

References 11 publications

The Design of Low Noise Amplifiers in Deep Submicron CMOS Processes: A Convex Optimization Approach

The Design of Low Noise Amplifiers in Deep Submicron CMOS Processes: A Convex Optimization Approach

Lumped-Element Wilkinson Power Combiners Using Reactively Compensated Star/Delta Coupled Coils in 28-nm Bulk CMOS

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