1981
DOI: 10.1149/1.2127774
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Deep Levels Study in Float Zone Si Used for Fabrication of CCD Imagers

Abstract: The development of a better understanding of the origin of defects which affect device performance requires the characterization of deep levels in Si wafers at various stages of processing. This work reports the results of deep level measurements by standard DLTS (deep level transient spectroscopy) and the newly developed DSPS (derivative surface photovoltage spectroscopy) technique on float zone p‐type (10 Ωcm) Si wafers used for the fabrication of CCD imagers. The DSPS measurements revealed the presence of d… Show more

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Cited by 11 publications
(8 citation statements)
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“…The one most important material problem associated with the use of silicon wafers in LSI and VLSI circuits is control of crystallographic defects formation, which is closely related to the oxygen-precipitation kinetics during processing (1)(2)(3). Defects present in the device active area, especially those decorated by heavy metals (4,5), would give dark current generation sites, which could cause functionality failure or excessive leakage in integrated circuits (1). However, defects present in the bulk of a silicon wafer would have a beneficial effect on circuit performance by acting as a gettering site for contamination, which otherwise would precipitate in the active area of the circuit leading to defect formation and/or decoration (1)(2)(3)(6)(7)(8).…”
mentioning
confidence: 99%
“…The one most important material problem associated with the use of silicon wafers in LSI and VLSI circuits is control of crystallographic defects formation, which is closely related to the oxygen-precipitation kinetics during processing (1)(2)(3). Defects present in the device active area, especially those decorated by heavy metals (4,5), would give dark current generation sites, which could cause functionality failure or excessive leakage in integrated circuits (1). However, defects present in the bulk of a silicon wafer would have a beneficial effect on circuit performance by acting as a gettering site for contamination, which otherwise would precipitate in the active area of the circuit leading to defect formation and/or decoration (1)(2)(3)(6)(7)(8).…”
mentioning
confidence: 99%
“…wafer thickness (around 525 ~m), it is not surprising that the diffusion length measured at the back of a SIMOX wafer corresponds to the concentration of heavy metals which are implanted into the front of a SIMOX wafer. It is well known that heavy metal precipitates contribute to defect nucleation and decoration (12)(13)(14)(15). These defects cause excessive junction leakage (8,(16)(17)(18).…”
Section: Discussionmentioning
confidence: 99%
“…Manuscript submitted May 7, 1986; revised manuscript received Aug. 2, 1986. This was Paper 418 presented at the Las Vegas, NV, Meeting of the Society, Oct. [13][14][15][16][17][18]1985.…”
Section: Discussionmentioning
confidence: 99%
“…Mechanical strength.--The mechanical strength of silicon wafers affects breakage (line yield) of wafers thinned to 10 ~m and susceptibility of silicon to generation of slip Heat-treatments involved during processing and virgin wafer characteristics and dislocations. The amount of low contrast white spots/line failures is related to the amount of dislocations and their decoration by heavy metals (14). In addition, the mechanical strength of silicon wafers can also affect resolution failures.…”
Section: Defect Originmentioning
confidence: 99%
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