Deep insight into linearity and NQS parameters of tunnel FET with emphasis on lateral straggle

Abstract

Tunnel field-effect transistor (TFET) is considered to have superior device performance compared with DG-metal-oxide-semiconductor FET in terms of reduced off-state current and lower subthreshold swing. However, performance of a device solely depends on the accuracy in the fabrication process. This work presents a systematic methodology in small-signal-radio-frequency (RF) and linearity domain to analyse the effect of variation in lateral straggle caused by the variation tilt angle during ion implantation process. From previously published researches, it is intuitively established fact that the accurate evaluation of intrinsic components and estimation of linearity in short channel devices is crucial to access the range of application of the device. In this work, the authors have investigated the RF intrinsic parameter performances of a silicon double gate TFET having variation in lateral straggle from 1 to 5 nm. This study includes the analysis of nonquasi-static RF bias-dependent parameters such as intrinsic capacitances (C gs , C gd), gate-to-drain intrinsic resistance (R gd) and intrinsic time delay (t). Similarly, the device linearity and reliability are investigated here in terms of higher-order transconductances (g m2 and g m3), VIP 2 , VIP 3 , IMD 3 , IIP 3 and 1 dB compression point.

Design and optimization of vertical nanowire tunnel FET with electrostatic doping

“…Table 2 shows the Comparison of the linearity parameters of the proposed device (having L D = 20 nm, L C = 20 nm & GWF = 4.2 eV) with the data already reported. Here IIP3 & VIP3 of the proposed device are higher, and IMD3 is lower than the other devices [30][31][32] with the lower value of VIP2. Thus the proposed device Inner-Gated NWTFET [36], Dual Material Gate Heterogeneous Dielectric Vertical TFET [37], GAA Nanowire FET [38], Multi Bridge channel FET [39] and Nanosheet FET [40] are compared with proposed device Electrostatically doped Vertical Nanowire TFET & it is observed that E-VNWTFET is having better I ON /I OFF, Lower DIBL and better subthreshold slope than most of the devices.…”

“…The device dimensions are scaled down, but due to the scaling the output signal can have noise; that is why it is important to analyse the linearity parameters VIP2, VIP3, IIP3 & IMD3 [29][30][31][32][33][34] of the device. Figures 10(a) & (b) shows the variation VIP2/VIP3 for V GS respectively.…”

Analysis on effect of lateral straggle on analog, high frequency and DC parameters in Ge‐source DMDG TFET

“…Koley et al highlighted that RF/analog parameters of symmetric and asymmetric DG MOSFET is improved with increased in σ 26 . It is also reported that RF/analog and linearity behavior of DG TFET is suppressed with rise in σ value 27,28 . Over course of time, analysis on effect of σ on RF/analog characteristic are presented in gate modulated 29 and hetero‐stacked TFETs 30 .…”

“…26 It is also reported that RF/analog and linearity behavior of DG TFET is suppressed with rise in σ value. 27,28 Over course of time, analysis on effect of σ on RF/analog characteristic are presented in gate modulated 29 and hetero-stacked TFETs. 30 Recently, the effect of source/drain gradient for the variation in lateral straggle parameter in terms of DC and RF performance is highlighted in Ge epitaxial DG TFET.…”

Dual‐channel trench‐gate tunnel FET for improved ON‐current and subthreshold swing

“…A TFET can deliver the SS values smaller than that of a conventional MOSFET ( 60 mV/decade at room temperature) [1]. In the recent past, several research efforts have been made to improve the performance of TFETs [5–13]. Despite the excellent switching performance and reduced , the TFETs suffer from low ON‐state current () which restricts the use of TFETs for commercial applications.…”