Dedicated Hardware Architecture for Partially Mapped Crossover

Abstract

This paper discusses new dedicated hardware architecture for partially mapped crossover (PMX). The proposed architecture introduces a new PMX algorithm which is suitable for hardware. It creates the matching-table using a register as preprocessing. The matching-table reduces the number of steps for comparison processing which is required in PMX algorithm. Thus, the proposed architecture requires only one clock cycle for the comparison processing, and achieves the high speed processing. Simulation results show that the proposed architecture achieved five times more high-speed processing than conventional PMX on average.