Decreasing the Off-Current for Vertical TFT by Using an Insulating Layer between Source and Drain

Abstract

A novel polysilicon vertical thin film transistor (VTFT) has been fabricated based on a low-temperature (T≤600°C) process. This new structure eliminates the large overlapping area between source and drain, and thus reduced the off-current and increased the I on /I off ratio. The technologically key point lies in the introduction of an insulating layer between source and drain, and the electrical properties of the fabricated VTFTs using different insulating layers are compared. These first results highlight that the SiO 2 insulating layer shows great advantages over the Si 3 N 4 insulating layer. The reduced off-current has revealed some potential applications for high density integration and high drive current.

(Invited) Towards Higher Integration Thin Film Technology by Involving P-Type and N-Type Vertical Channel Thin Film Transistors

“…But, due to m difficult to introduce in large area technologi cked films, an undoped polysilicon film is depo ractice, the film has a good aspect ratio. The thi current by decreasing drastically the overlapp ulation with ATLAS and ATHENA modules (F eters such as carrier mobilities, gate oxide thi the I on /I off ratio as shown Figure 10 [29][30][31]. sign of a new fabrication process.…”

“…Figure 11 (a) is a scan that includes four finger Figure 11 (b) gives details of SiO 2 or Si 3 N 4 and in or the adopted solution was approximately the length o Figure 11. New architectur fabricated device [31], (b) silicon oxide barrier (SiO effect that can occurs simil is deposited above the thin channels.…”

“…The profile of the sidewall is optimized with a minimum embossment on the sidewall for the second structure. Figure 13 shows the transfer characteristics of two VTFT involving silicon oxide barriers [31][32]. Curve (a) corresponds to the best previous VTFT without insulating barrier; in this case the I on /I off ratio is lower than 10 3 .…”

Vertical Conduction in the New Field Effect Transistors: p-Type and n-Type Vertical Channel Thin Film Transistors

“…On left the shape of the sidewall for silicon oxide barrier layer. On right, the optimization of the sidewalls for the silicon nitride barrier layer (After P. Zhang et al [33][34] The second problem to solve was the location of channel region. In practice, the channel polysilicon layer is deposited once the sidewalls are fabricated.…”

“…b) SEM top view of a four tooth comb that contains 8 channels in parallel. The structure was electrically characterized (After P. Zhang et al33 ).…”