Decreasing Size, Increasing Battery Life: A Wide-Band, Low-Noise Amplifier for 5G Multistandard Broadband Communications

Heinrichs, Markus; Bark, Niklas; Kronberger, Rainer

doi:10.1109/mmm.2017.2779683

Cited by 4 publications

(2 citation statements)

References 2 publications

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“…The broadband wireless communication system is expected to provide flexible delivery data over multiple platform technologies [2]. Hence, wideband or multi band transceivers become more familiar in the wireless communication fields [3].…”

Section: Introductionmentioning

confidence: 99%

A 2.3/3.3-GHz Dual Band Low Noise Amplifier Using Switchable Load Inductor in 0.18-um CMOS Technology

Kurniawan

Chen

2019

MST

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In this paper, the dual band low noise amplifier is designed in 0.18-μm CMOS technology. By combining the proposed switchable load inductor for gain controlling and the conventional inductive source degeneration topology, narrow band gain and good impedance matching are achieved at 2.3/3.3-GHz frequency bands. The new mathematical analysis of low noise amplifier design is derived to define the component parameters of the proposed circuits. The proposed low noise amplifier exhibits gain of 17.18 dB and 15.5 dB, and noise figure of 2.67 dB and 2.52 dB at the two frequency bands, respectively. AbstrakPenguat Derau Rendah Pita Ganda 2,3/3,3-GHz dengan Menggunakan Induktor Beban yang dapat Dialihkan di dalam Teknologi CMOS 0,18-m. Pada paper ini, dual band low noise amplifier didesain menggunakan teknologi CMOS 0.18-μm. Dengan mengkombinasikan usulan switchable load inductor sebagai pengendali gain dan topologi konvensional inductive source degeneration, gain dengan lebar yang sempit dan kesesuaian impedansi yang baik dapat dicapai pada frekuensi 2.3/3.3-GHz. Analisa matematika rangkaian yang baru pada desain rangkaian low noise amplifier telah dijabarkan untuk menentukan parameter-paramter komponen rangkaian yang diusulkan. Low noise amplifier yang didesain menghasilkan gain sebesar 17.18 dB dan 15.5 dB, serta noise figure sebesar 2.67 dB dan 2.52 dB pada dua pita frekuensi, secara berurutan.

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Section: Introductionmentioning

confidence: 99%

A 2.3/3.3-GHz Dual Band Low Noise Amplifier Using Switchable Load Inductor in 0.18-um CMOS Technology

Kurniawan

Chen

2019

MST

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“…As per the norms of FCC (Federal Communications Commission), the unlicensed frequency band is 3.1-10. 6 GHz [1]. The requirement of the high data rate in any communication is the primary focus which can be achieved using UWB band.…”

Section: Introductionmentioning

confidence: 99%

Design of High-Gain CG–CS 3.1–10.6 GHz UWB CMOS Low-Noise Amplifier

Kalra

Kumar

Chaturvedi

2018

Lecture Notes in Electrical Engineering

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A high-gain low-power CMOS low-noise amplifier is simulated using TSMC 0.18-μm CMOS technology. The cascade topology is used to get the highgain and low-noise figure value. The source degeneration technique is used for the wideband matching. The circuit is simulated for 3.1-10.6 GHz in ultawideband. The simulated results show the maximum gain of 21.574 dB at 6.378 GHz and positive gain maintained during the entire frequency range. The highest noise figure value is 4.311 dB at 7.662 GHz, and the lowest value is 2.477 dB at 3.1 GHz. The matching circuit at input and output terminals shows the input return loss of 22.262 dB at 10.38 GHz, while the output return loss of 30.936 dB at 4.1 GHz. The circuit is simultaed at 1.2 V which draws the power consumption of 17.734 mW. The designed circuit shows the optimum value of gain, noise figure, matching and power consumption.

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Component Linearity and Power Efficiency: A Sub-Six 5G Flexible Low-Interference Receiver

Heinrichs

Kronberger

2020

IEEE Microwave

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Decreasing Size, Increasing Battery Life: A Wide-Band, Low-Noise Amplifier for 5G Multistandard Broadband Communications

Cited by 4 publications

References 2 publications

A 2.3/3.3-GHz Dual Band Low Noise Amplifier Using Switchable Load Inductor in 0.18-um CMOS Technology

A 2.3/3.3-GHz Dual Band Low Noise Amplifier Using Switchable Load Inductor in 0.18-um CMOS Technology

Design of High-Gain CG–CS 3.1–10.6 GHz UWB CMOS Low-Noise Amplifier

Component Linearity and Power Efficiency: A Sub-Six 5G Flexible Low-Interference Receiver

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