Decrease of Parasitic Capacitance for Improvement of RF Performance of Multi-finger MOSFETs in 90-nm CMOS Technology

Abstract

Abstract-In this paper, the RF characteristics of multi-finger MOSFETs were improved by decreasing the parasitic capacitance in spite of increased gate resistance in a 90-nm CMOS technology. Two types of device structures were designed to compare the parasitic capacitance in the gate-to-source (C gs ) and gate-to-drain (C gd ) configurations. The radio frequency (RF) performance of multi-finger MOSFETs, such as cut-off frequency (f T ) and maximum-oscillation frequency (f max ) improved by approximately 10% by reducing the parasitic capacitance about 8.2% while maintaining the DC performance.