2016
DOI: 10.1109/ted.2016.2614275
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Circuit Level Layout Optimization of MOS Transistor for RF and Noise Performance Improvements

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Cited by 8 publications
(6 citation statements)
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“…As shown in Figure 8, the type B transistor can realize the highest g m , which indicates that a low NF min can be realized. 33 The high g m , moderate C gs , and C gd with low r g also contribute to a high f T and f max as shown in Equations 1 and 2.…”
Section: Mm-wave Transistor-layout Techniques For Wideband Lnamentioning
confidence: 96%
See 4 more Smart Citations
“…As shown in Figure 8, the type B transistor can realize the highest g m , which indicates that a low NF min can be realized. 33 The high g m , moderate C gs , and C gd with low r g also contribute to a high f T and f max as shown in Equations 1 and 2.…”
Section: Mm-wave Transistor-layout Techniques For Wideband Lnamentioning
confidence: 96%
“…The input matching network with three-coil transformer different performances, which can be used in different applications. [33][34][35][36] The gate contacting stacks can be generally divided into two types, the single-end type, and the double-end type. In the single-end type, the gate path is connected from a single-end of the poly-gate to the top or subtop metal layer by contacts and metal vias, 34 while in double-end type, both ends of the poly-gate are connected out in parallel.…”
Section: Mm-wave Transistor-layout Techniques For Wideband Lnamentioning
confidence: 99%
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