Decoupling Dynamic Information Flow Tracking with a dedicated coprocessor

Kannan, Hari; Dalton, Michael; Kozyrakis, Christos

doi:10.1109/dsn.2009.5270347

Cited by 60 publications

(63 citation statements)

References 13 publications

(34 reference statements)

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“…However, performing invasive hardware modifications to existing processor designs presented a major obstacle in deploying information flow tracking in practice due to the high hardware design and verification costs. The DIFT co-processor [25] proposed to reduce these costs by performing DIFT in a small decoupled co-processor. The DIFT co-processor was shown to be able to provide the same degree of security as the most complete integrated DIFT architecture, had lower performance overheads, and required fewer invasive changes to the baseline processing core.…”

Section: A Hardware-based Run-time Monitoringmentioning

confidence: 99%

High-performance parallel accelerator for flexible and efficient run-time monitoring

Deng

Suh

2012

IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012)

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This paper proposes Harmoni, a high performance hardware accelerator architecture that can support a broad range of run-time monitoring and bookkeeping functions. Unlike custom hardware, which offers very little configurability after it has been fabricated, Harmoni is highly configurable and can allow a wide range of different hardware monitoring and bookkeeping functions to be dynamically added to a processing core even after the chip has already been fabricated. The Harmoni architecture achieves much higher efficiency than software implementations and previously proposed monitoring platforms by closely matching the common characteristics of run-time monitoring functions that are based on the notion of tagging. We implemented an RTL prototype of Harmoni and evaluated it with several example monitoring functions for security and programmability. The prototype demonstrates that the architecture can support a wide range of monitoring functions with different characteristics. Harmoni takes moderate silicon area, has very high throughput, and incurs low overheads on monitored programs.

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Section: A Hardware-based Run-time Monitoringmentioning

confidence: 99%

High-performance parallel accelerator for flexible and efficient run-time monitoring

Deng

Suh

2012

IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012)

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“…al. proposed a hardware system for dynamic information flow tracking (DIFT) [6]. They used a customized processor to run DIFT and disposed it on the L2 cache.…”

Section: Related Workmentioning

confidence: 99%

Customized Core Layout: A Case Study on Dual-Core Dynamic Binary Translation System

Shen

Wang

et al. 2014

2014 IEEE International Conference on Computer and Information Technology

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High efficient hardware accelerators are customized to improve the performance of applications from special domains. In this paper, we try to answer the question of where should we integrate a customized processor core to accelerate an application via comparing the performance on different multi-core platforms. We select dynamic binary translation as example application. First, we establish a performance model for software DBT system and describe its design space. Then, we build an abstract architecture of dualcore DBT system, and list three possible locations to integrate a customized accelerator. Finally, we did simulation on the three platforms with the customized DBT core integrated in the different locations, and discussed the result. By the result of the simulation, we have proved that the DBT can be speedup by the dual-core platform, and the platform 2 with a customized core on DIMM shows the best performance(about 48% compared with the single core DBT).

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“…Table I compares features in existing works that are based on the same off-core approach as our proposed architecture ARMHEx. [2]- [4] implemented DIFT using a softcore processor. In these works, the CPU pipeline is modified in order to export information needed for DIFT.…”

Section: Related Workmentioning

confidence: 99%

ARMHEx: A hardware extension for DIFT on ARM-based SoCs

Wahab¹,

Cotret²,

Allah³

et al. 2017

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

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Abstract-Security is a major issue nowadays for the embedded systems community. Untrustworthy authorities may use a wide range of attacks in order to retrieve critical information. This paper introduces ARMHEx, a practical solution targeting DIFT (Dynamic Information Flow Tracking) on ARM-based SoCs (e.g. Xilinx Zynq). Current DIFT implementations suffer from two major drawbacks. First, recovering required information for DIFT is generally based on software instrumentation leading to high time overheads. ARMHEx takes profit of ARM CoreSight debug components and static analysis to drastically reduce instrumentation time overhead (up to 90% compared to existing works). Then, security of the DIFT hardware extension itself is not considered in related works. In this work, we tackle this issue by proposing a solution based on ARM Trustzone.

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Decoupling Dynamic Information Flow Tracking with a dedicated coprocessor

Cited by 60 publications

References 13 publications

High-performance parallel accelerator for flexible and efficient run-time monitoring

High-performance parallel accelerator for flexible and efficient run-time monitoring

Customized Core Layout: A Case Study on Dual-Core Dynamic Binary Translation System

ARMHEx: A hardware extension for DIFT on ARM-based SoCs

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