Decoupling capacitor planning and sizing for noise and leakage reduction

Wong, Eric; Minz, J.R.; Lim, Sung Kyu

doi:10.1145/1233501.1233580

Cited by 11 publications

(13 citation statements)

References 20 publications

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“…We first compare our results to an existing work that is based on "effective decap distance" [5] 5 . We use the 250nm technology parameters used in [5].…”

Section: B Decap Planning Resultsmentioning

confidence: 99%

“…We use the method presented in [4] and [5] to calculate IR-drop and Ldi/dt noise from a given floorplan. A uniform RLC-mesh is used to model the P/G network.…”

Section: Noise Analysismentioning

confidence: 99%

“…The objective is to minimize the floorplan area while suppressing the power supply noise below the specified limit. The authors of [5] presents a circuit model to allow non-adjacent decap access instead of only adjacent decap in [4]. Iteration of linear programming in decap planning is applied in [6], [7].…”

Section: Introductionmentioning

confidence: 99%

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Decoupling capacitor planning with analytical delay model on RLC power grid

Ye¹,

Lim²

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-Decoupling capacitors (decaps) are typically used to reduce the noise in the power supply network. Because the delay of gates and interconnects is affected by the supply voltage level, decaps can be used to improve the circuit performance as well. In this paper, we present the analytical delay model under IR drop, Ldi/dt noise, and decaps to study how decaps affect both the gate and interconnect delay. Given a floorplanning solution, we study how to allocate the whitespace for decap insertion so that the delay is minimized under the given noise and area constraint. We employ the Sequential Linear Programming method to solve the non-linear whitespace allocation problem. Our experimental results show that intelligent decap allocating decap makes further delay reduction possible without adding any additional decap.

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“…We first compare our results to an existing work that is based on "effective decap distance" [5] 5 . We use the 250nm technology parameters used in [5].…”

Section: B Decap Planning Resultsmentioning

confidence: 99%

“…We use the method presented in [4] and [5] to calculate IR-drop and Ldi/dt noise from a given floorplan. A uniform RLC-mesh is used to model the P/G network.…”

Section: Noise Analysismentioning

confidence: 99%

See 1 more Smart Citation

Decoupling capacitor planning with analytical delay model on RLC power grid

Ye¹,

Lim²

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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“…In the recent past, the CMOS decap allocation and optimization problem has been investigated by numerous researchers for 2D [9], [11]- [16], [18] and 3D technologies [17]- [19].…”

Section: Introductionmentioning

confidence: 99%

Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors

Zhou

Sridharan

Sapatnekar

2009

2009 Asia and South Pacific Design Automation Conference

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Abstract-In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise problem, already a major issue in 2D, is even more severe in 3D. CMOS decoupling capacitors (decaps) have been used effectively for controlling power grid noise in the past, but with technology scaling, they have grown increasingly leaky. As an alternative, metal-insulator-metal (MIM) decaps, with high capacitance densities and low leakage current densities, have been proposed. In this paper, we explore the tradeoffs between using MIM decaps and traditional CMOS decaps, and propose a congestion-aware 3D power supply network optimization algorithm to optimize this tradeoff. The algorithm applies a sequence-of-linear-programs based method to find the optimum tradeoff between MIM and CMOS decaps. Experimental results show that power grid noise can be more effectively optimized after the introduction of MIM decaps, with lower leakage power and little increase in the routing congestion, as compared to a solution using CMOS decaps only.

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“…CCF-0546382 and the Interconnect Focus Center (IFC). Previous work on power supply issues related to 3D stacking has examined the problem mainly from a packaging perspective [2], [3]. Other works that have investigated the impact of 3D stacking have limited their scope to systems with only a small number of tiers [4], [5], [6].…”

Section: Introductionmentioning

confidence: 99%

A study of stacking limit and scaling in 3D ICs: an interconnect perspective

Healy

Lim

2009

2009 59th Electronic Components and Technology Conference

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An examination of large-scale stacking of 3D integrated ICs from a power-supply and thermal reliability perspective is presented. Noise characteristics and scaling issues related to through-silicon-via (TSV) size and pitch as well as other power-supply topology characteristics are included. Thermal simulations are carried out assuming the use of micro-fluidic heatsinks to provide cooling to systems with power dissipation of up to 525 watts and 46 integrated silicon tiers. Results indicate that these large systems are feasible given sufficient planning. Power-delivery-bump pitch is identified as the most important factor influencing IR-drop and dynamic noise. Contact resistance also may become a major limiting factor. I. IntroductionThe shift to the multi-core era has increased demand on the memory bandwidth of high performance processor systems. 3D integration of memory and processors has emerged as a potential solution to the memory bandwidth problem. However, there are several unanswered questions regarding 3D integration. In this work we study integration scaling from a power-supply and thermal perspective. As the number of tiers in a 3D system increase, the uppermost tiers become separated from the power supply bumps by increasing resistance and inductance. The cause of these parasitics is the through-silicon vias (TSVs) that provide communication between tiers. Additionally, increasing integration quickly raises the volumetric power density of the IC stack.The largest factor creating transient noise is the so-called "first droop" noise that results from the interaction of the inductance in the package and the on-chip decap during sleep transitions. Power gating due to sleep transitions causes large transient changes in the current demand in the power supply network. In the case of 3D systems the TSVs add inductance of their own to that which naturally exists in the package.Thermal impacts are a major factor that must be considered when designing 3D systems. For the purpose of maximum 3D integration studies standard air-cooled heatsinks will be unable to cope with the power density of these systems. Recent work has focused on implementing micro-fluidic channels [1] onto the backs of 3D stacked ICs for the purpose of removing heat using liquid-phase fluids. The heat removal capacity of these systems is very promising. In this work we assume that microfluidic heatsinks are used to dissipate heat, and design our power distribution model around this assumption.

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Decoupling capacitor planning and sizing for noise and leakage reduction

Cited by 11 publications

References 20 publications

Decoupling capacitor planning with analytical delay model on RLC power grid

Decoupling capacitor planning with analytical delay model on RLC power grid

Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors

A study of stacking limit and scaling in 3D ICs: an interconnect perspective

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