Decimal Floating-Point Multiplication Via Carry-Save Addition

A parallel IEEE P754 decimal floating-point multiplier

“…Due to the range of each operand and the method in which the shift amount is determined, rounding overflow cannot occur in this design. To learn more about why this is true, the reader is referred to [15].…”

“…This design allows trade-offs between clock frequency and overall latency by adding pipeline stages. As compared to the sequential design in [15], an 11-stage pipelined version of our design has similar clock speed, significantly reduced latency (11 vs. 21 cycles), and one result per cycle throughput, while incurring a substantial 371% increase in area. To the best of our knowledge, this is the first published design of a parallel decimal floating-point multiplier that is compliant with IEEE P754.…”

“…This multiplier generates a sufficient subset of multiplicand multiples and then selects all the partial-products in parallel based on the digits of the multiplier operand. Only a few designs supporting DFP multiplication have been presented [3,2,15]. However, to our knowledge currently only the iterative multiplier from [15] complies with the IEEE P754 standard.…”

“…Only a few designs supporting DFP multiplication have been presented [3,2,15]. However, to our knowledge currently only the iterative multiplier from [15] complies with the IEEE P754 standard.…”

“…This paper presents a parallel DFP multiplier based on a parallel fixed-point multiplier [1] and a previous implementation of a DFP multiplier [15]. The novelty of the design is that it is the first parallel DFP multiplier, offering low latency, high throughput, and IEEE P754 compliance.…”