Deadlock-free generic routing algorithms for 3-dimensional Networks-on-Chip with reduced vertical link density topologies

Ying, Haoyuan; Jaiswal, AK; Hollstein, Thomas

doi:10.1016/j.sysarc.2013.03.005

Cited by 8 publications

(8 citation statements)

References 19 publications

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“…Many of these algorithms need to follow specific rules that require TSVs to be placed in a specific manner and often have further constraints as to which TSVs can be selected during runtime. In [13], the authors propose two routing algorithms named SBSM (Source-Based Shortest Manhattan) and DBSM (Destination-Based Shortest Manhattan). SBSM selects the vertical link that is the closest to the source node, whereas DBSM selects the vertical link that is the closest to the destination.…”

Section: Related Workmentioning

confidence: 99%

“…if SameCol is empty then (10) ( , ) = random elevator from Min (11) else (12) ( , ) = random elevator from SameCol (13) end if…”

Section: Outputmentioning

confidence: 99%

“…for all ( , ) ∈ do (10) = 0 (11) if > then (12) add East to (13) end if (14) if < then (15) add West to (16) end if (17) if > then (18) add North to (19) end if (20) if < then (21) add South to (22) end if…”

Section: Inputmentioning

confidence: 99%

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A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips

et al. 2017

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3D integration can greatly benefit future many-cores by enabling low-latency three-dimensional Network-on-Chip (3D-NoC) topologies. However, due to high cost, low yield, and frequent failures of Through-Silicon Via (TSV), 3D-NoCs are most likely to include only a few vertical connections, resulting in incomplete topologies that pose new challenges in terms of deadlockfree routing and TSV assignment. The routers of such networks require a way to locate the nodes that have vertical connections, commonly known as elevators, and select one of them in order to be able to reach other layers when necessary. In this paper, several alternative TSV selection strategies requiring a constant amount of configurable bits per router are introduced. Each proposed solution consists of a configuration algorithm, which provides each router with the necessary information to locate the elevators, and a routing algorithm, which uses this information at runtime to route packets to an elevator. Our algorithms are compared by simulation to highlight the advantages and disadvantages of each solution under various scenarios, and hardware synthesis results demonstrate the scalability of the proposed approach and its suitability for cost-oriented designs.

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Section: Related Workmentioning

confidence: 99%

“…if SameCol is empty then (10) ( , ) = random elevator from Min (11) else (12) ( , ) = random elevator from SameCol (13) end if…”

Section: Outputmentioning

confidence: 99%

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A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips

et al. 2017

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“…Therefore, we present a adaptive routing algorithm based on the dynamic quadrant partitioning (DQP) method, which is valid for irregular vertical link distributed 3D NoCs and can maintain the system performance in comparison to the full vertical link connected 3D NoC with ZXY routing algorithm by reducing 40% vertical links number. Also we have compared the DQP adaptive routing with our previous work [13], the static routing algorithm in reduced vertical link topologies 3D NoCs, the results show that up to 10.9% improvement of the latency. Also the DQP adaptive routing algorithms has quite few hardware implementation overhead (1.4% in area) in comparison to the work [13].…”

Section: Introductionmentioning

confidence: 97%

“…Also we have compared the DQP adaptive routing with our previous work [13], the static routing algorithm in reduced vertical link topologies 3D NoCs, the results show that up to 10.9% improvement of the latency. Also the DQP adaptive routing algorithms has quite few hardware implementation overhead (1.4% in area) in comparison to the work [13].…”

Section: Introductionmentioning

confidence: 97%

Dynamic quadrant partitioning adaptive routing algorithm for irregular reduced vertical link density topology 3-Dimensional Network-on-Chips

Ying

Hollstein

2014

2014 International Conference on High Performance Computing &Amp; Simulation (HPCS)

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3-Dimensional Networks-on-Chips (3D NoCs) are proposed as the next generation interconnect infrastructure for multi/many core embedded systems due to the high performance characteristics and scalability. However the heat and thermal issues in 3D NoCs are critical. Reducing the vertical links between dies becomes can be one of the proper solutions, but the 3D NoC system performance can be harmed due to the less number of possible vertical links. In order to find the best trade-off point between the vertical links reduction and 3D NoC performance, in this paper, we demonstrate a dynamic quadrant partitioning (DQP) adaptive routing algorithm for 3D NoCs with irregular reduced vertical link density topologies, which can improve the system performance (latency max. 10.9% and energy max. 24.1%) in comparison to deterministic routing algorithm with the same vertical link number configurations. Also our DQP routing algorithm can maintain the system performance in comparison to full vertical link connection running dimensionorder deterministic routing algorithm (ZXY) by reducing 40% vertical links number. The comparison results are demonstrated with different benchmark applications and random generated task graphs.

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An Overview of Multicast Routing Algorithms in Network on Chip

Velayudham¹,

Rajagopal

Kathirvel³

et al. 2021

Learning and Analytics in Intelligent Systems

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Deadlock-free generic routing algorithms for 3-dimensional Networks-on-Chip with reduced vertical link density topologies

Cited by 8 publications

References 19 publications

A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips

A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips

Dynamic quadrant partitioning adaptive routing algorithm for irregular reduced vertical link density topology 3-Dimensional Network-on-Chips

An Overview of Multicast Routing Algorithms in Network on Chip

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