DDMPs: self-timed super-pipelined data-driven multimedia processors

Terada, Hiroaki; Miyata, S.; Iwata, Makoto

doi:10.1109/5.740021

Cited by 38 publications

(29 citation statements)

References 21 publications

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“…A piece of data, which is termed packet in the STP, is transferred locally between adjacent pipeline stages. This local data transfer is controlled based on a bundled data transfer scheme using transfer request (send) and acknowledge (ack) signals [1]. The C element is designed to assert its send signal to the next stage and its gate open signal only when the input send and ack signals are coincident.…”

Section: Self-timed Pipelinementioning

confidence: 99%

“…However, with an increase in the clocking rate, the structure suffers from the excessive power consumption and signal integrity problems associated with synchronous clock distribution. In order to solve these problems simultaneously, a basic selftimed pipeline (STP) structure has been utilized to develop a commercial data-driven multimedia processor (DDMP) [1] and a unique self-timed functional module [2]. This paper proposes an advanced scheme of interacting self-timed pipelines to fully utilize giga-transistors on a die area.…”

Section: Introductionmentioning

confidence: 99%

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Interacting Self-Timed Pipelines and Elementary Coupling Control Modules

Komatsu

Sannomiya

Iwata

et al. 2009

IEICE Trans. Fundamentals

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SUMMARYThe self-timed pipeline (STP) is one of the most promising VLSI/SoC architectures. It achieves efficient utilization of tens of billions of transistors, consumes ultra low power, and is easy-to-design because of its signal integrity and low electro-magnetic interference. These basic features of the STP have been proven by the development of selftimed data-driven multimedia processors, DDMP's. This paper proposes a novel scheme of interacting self-timed (clockless) pipelines by which the various distributed and interconnected pipelines can achieve highly functional stream processing in future giga-transistor chips. The paper also proposes a set of elementary coupling control modules that facilitate various combinations of flow-thru processing between pipelines, and then discusses the practicality of the proposed scheme through the LSI design of application modules such as a priority-based queue, a mutual interconnection network, and a pipelined sorter.

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Section: Self-timed Pipelinementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Interacting Self-Timed Pipelines and Elementary Coupling Control Modules

Komatsu

Sannomiya

Iwata

et al. 2009

IEICE Trans. Fundamentals

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“…Asynchronous VLSI design has been gaining a new popularity since the end of the 80's. Representative results in asynchronous microprocessor design have been achieved [6,7,8,9,10,11,14,15]. Most designs address high performance with reduced power consumption, and utilize specialized techniques which involve layout topology and physical delay assumptions.…”

Section: Introductionmentioning

confidence: 98%

Delay-insensitive synthesis of the MCS 251 microcontroller core for low power applications

Gloria

Olivieri²,

Palma³

1999

Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium

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We present the design of an asynchronous microcontroller core featuring binary compatibility with the MCS 251 family. The work is involved in a specific application project targeting portable electromagnetic measurement systems with very low power consumption. Delay insensitivity was chosen to allow a fast design of complex but safe asynchronous circuits, by automatic synthesis and independency of layout topology. On the other hand, unconventional logic cells must be employed, and special features have been introduced in the synthesis tool to dominate the circuit area, estimating the power consumption and interfacing with more conventional CAD flows. A preliminary set of results is illustrated in detail.

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“…The fabricated processor exhibits impressive performance and power consumption, operating at a speed of 8600 Million Operations per Second and with power consumption less than 1 watt. The processor consists of 8 programmable, data-driven processing elements connected by an elastic router [65].…”

Section: Asynchronous Processorsmentioning

confidence: 99%