Dataflow machine architecture

Veen, Arthur H.

doi:10.1145/27633.28055

Cited by 222 publications

(130 citation statements)

References 20 publications

(15 reference statements)

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…MDF is one of several large grain data flow models [1][3] that expand on traditional data flow [22]. The salient features of MDF are that it incorporates the notion of state, adds the ability to dynamically create graphs, and provides coarse grained actors.…”

Section: Mentat Execution Modelmentioning

confidence: 99%

Exploiting Data-Flow for Fault-Tolerance in a Wide-Area Parallel System

Nguyen-Tuong¹,

Grimshaw²,

Hyett³

1996

View full text Add to dashboard Cite

Wide-area parallel processing systems will soon be available to researchers to solve a range of problems. In these systems, it is certain that host failures and other faults will be a common occurrence. Unfortunateb, most parallel processing systems have not been designed with fault-tolerance in mind. Mentat is a high-performance objec t-oriented parallel processing system that is based on an extension of the data-flow model. The functional nature of data-flow enabies both parallelism and faulttolerance. In this paper, we exploit the data-flow underpinning of Mentat to provide easy-to-use and transparent fault-tolerance. We present results on both a small-scale network and a wide-area heterogeneous environment that consists of three sites: the National Center for Supercomputing Applications, the University of Mrginia and the NASA Langley Research Center.

show abstract

Section: Mentat Execution Modelmentioning

confidence: 99%

Exploiting Data-Flow for Fault-Tolerance in a Wide-Area Parallel System

Nguyen-Tuong¹,

Grimshaw²,

Hyett³

1996

View full text Add to dashboard Cite

show abstract

“…Unlike dynamic model, there is disadvantage of the static dataflow computer architecture in impossibility to use dynamic forms of parallelism, including loops and recursion. Dynamic data flow model allows dynamic forms of parallelism, both loop and recursive, that appear in the time of program execution [1,2,3,4,5,6,7].…”

Section: Introductionmentioning

confidence: 99%

Subgraph Colouring Technique for Computer with Data Driven Computation Model

Vokorokos¹,

Madoš²,

Ádám³

et al. 2013

AIP

View full text Add to dashboard Cite

Paper deals with the data driven computation control paradigm, which is alternative to the mainstream control flow model of program execution control. In the second part of the paper we are introducing computer architecture that is proposed at the Department of Computers and Informatics, Faculty of Electrical Engineering and Informatics, Technical University of Košice, according to the data driven computation control model with use of tile computing principles. In the final part of the paper, subgraph colouring technique that is unique characteristic of proposed computer architecture is described.

show abstract

“…Dataflow machines are all programmable computers of which the hardware is optimised for fine-grained data-driven parallel computing [87]. In general, a processing element of a classical dataflow machine is composed as follows.…”

Section: Dataflow Machinesmentioning

confidence: 99%

“…Dynamic dataflow machines allow, in contrast to static dataflow machines, multiple tokens per arc. This can be achieved by either code-copying or tagged tokens, for more details, see [87]. Dynamic dataflow machines potentially provide the highest level of parallelism [87].…”

Section: -Dataflow Machinesmentioning

confidence: 99%

See 1 more Smart Citation

A fine-grained parallel dataflow-inpsired architecture for streaming applications

Niedermeier¹

View full text Add to dashboard Cite

This thesis was typeset using L A T E X, TikZ, and GNU Emacs. This thesis was printed by Gildeprint, The Netherlands. AbstractData-driven streaming applications are quite common in modern multimedia and wireless applications, like for example video and audio processing. The main components of these applications are Digital Signal Processing (DSP) algorithms.These algorithms are not extremely complex in terms of their structure and the operations that make up the algorithms are fairly simple (usually binary mathematical operations like addition and multiplication). What makes it challenging to implement and execute these algorithms efficiently is their large degree of fine-grained parallelism and the required throughput.DSP algorithms can usually be described as dataflow graphs with nodes corresponding to operations and edges between the nodes expressing data dependencies. On the edges, data travels in the form of tokens. A node fires as soon as all required input data has arrived at its input edge(s). One firing consists of consuming the input data (i.e. input tokens), executing the desired operation, and producing the output data (i.e. output tokens). Usually, input data to the dataflow graph is provided as a stream of tokens. As a consequence, a well-behaved dataflow graph keeps executing as long as input data arrives.To execute DSP algorithms efficiently while maintaining flexibility, coarse-grained reconfigurable arrays (CGRAs) can be used. CGRAs are composed of a set of small, reconfigurable cores, interconnected in e.g. a two dimensional array. Each core by itself is not very powerful, yet the complete array of cores forms an efficient architecture with a high throughput due to its ability to efficiently execute operations in parallel.To program CGRAs, usually an architecture-specific subset of C is defined which is then used to specify and implement algorithms on the respective CGRA. However, the C programming paradigm was not developed to specify algorithms that contain a large degree of fine-grained parallelism. Instead, it was designed to implement sequential algorithms on single-core architectures.In this thesis, we present a CGRA targeted at data-driven streaming DSP applications that contain a large degree of fine-grained parallelism, such as matrix manipulations or filter algorithms. Along with the architecture, also a programming language is presented that can directly describe DSP applications as dataflow graphs which are then automatically mapped and executed on the architecture. v viIn contrast to previously published work on CGRAs, the guiding principle and inspiration for the presented CGRA and its corresponding programming paradigm is the dataflow principle. Three main aspects can be named here:1. A DSP algorithm is represented as a dataflow graph with nodes corresponding to operations and edges between the nodes corresponding to data dependencies. 2. The configuration and execution principles of the cores in the architecture are based on dataflow principles, i.e. a core starts its executi...

show abstract

Dataflow machine architecture

Cited by 222 publications

References 20 publications

Exploiting Data-Flow for Fault-Tolerance in a Wide-Area Parallel System

Exploiting Data-Flow for Fault-Tolerance in a Wide-Area Parallel System

Subgraph Colouring Technique for Computer with Data Driven Computation Model

A fine-grained parallel dataflow-inpsired architecture for streaming applications

Contact Info

Product

Resources

About