Data Transfer and Storage Architecture Issues and Exploration in Multimedia Processors

Catthoor, Francky; Danckaert, Koen; Kulkarni, Chidamber; Omn√©s, Thierry

doi:10.1201/9780203908068.ch9

“…Indeed, these compilers automatically perform data distribution across banks, determine which access goes to which bank, and then schedule to avoid bank conflicts. The Data Transfer and Storage Exploration (DTSE) method from IMEC and the associated tools (ATOMIUM, ADOPT) are also a good mean to determine a convenient data mapping [9].…”

Section: Memory Aware Synthesismentioning

confidence: 99%

Memory aware HLS and the implementation of ageing vectors

Corre

¹

,

Senn

²

,

Julien

³

et al. 2004

Euromicro Symposium on Digital System Design, 2004. DSD 2004.

0

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We introduce a new approach to take into account the memory architecture and the memory mapping in behavioral synthesis. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We present a new strategy for implementing signals (ageing vectors). We formalize the maturing process and explain how it may generate memory conflicts over several iterations of the algorithm. The final Compatibility Graph indicates the set of valid mappings for every signal. Several experiments are performed with our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time.

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“…The difference is that the conflicts arise between logical addresses that are calculated over several successive iterations (2 in this example). @x [2] o is in concurrence with @x [0] o+1 , and x [3] o is in concurrence with @x [1] o+1 . The set of concurrent accesses SCA = {(0, 1), (1, 2), (2, 3), (3, 0)}.…”

Section: Implementing Ageing Vectorsmentioning

confidence: 99%

“…Indeed, these compilers automatically perform data distribution across banks, determine which access goes to which bank, and then schedule to avoid bank conflicts. The Data Transfer and Storage Exploration (DTSE) method from IMEC and the associated tools (ATOMIUM, ADOPT) are also a good mean to determine a convenient data mapping [3].…”

Section: Memory Aware Synthesismentioning

confidence: 99%

“…The data mapping is verified. The minimum number of banks is 2, and the only valid mapping with 2 banks is to place x[0] and x [2] in a bank, and x[1] and x [3] in another bank. …”

Section: Implementing Ageing Vectorsmentioning

confidence: 99%

“…Eventually, to calculate the logical address of x[0], we add (modulo N), to the logical address of x [3] in the preceding iteration, the weight f30 and the ageing factor k so that @x …”

Section: Implementing Ageing Vectorsmentioning

confidence: 99%

See 2 more Smart Citations

Memory accesses management during high level synthesis

Corre

¹

,

Senn

²

,

Bomel

³

et al. 2004

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS

View full text Add to dashboard Cite

We introduce a new approach to take into account the memory architecture and the memory mapping in behavioral synthesis. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We present a new strategy for implementing signals (ageing vectors). We formalize the maturing process and explain how it may generate memory conflicts over several iterations of the algorithm. The final Compatibility Graph indicates the set of valid mappings for every signal. Several experiments are performed with our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time.

show abstract

Statistical Performance Analysis and Estimation for Parallel Multimedia Processing

Li

¹

,

Achteren

²

,

Brockmeyer

³

et al. 2009

J Sign Process Syst Sign Image Video Technol

Self Cite

2

0

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When parallelizing complex multimedia processing on multiple processors, the stochastic timing behavior should be carefully studied. Although there are already many papers on the performance analysis of stochastic parallel system, they are not targeted on multimedia processing. In this paper, first we study H.264/AVC encoder (running on x86) and QSDPCM encoder (running on TI TMS32C62) to characterize important aspects of the stochastic timing behavior in complex multimedia processing applications. It is shown that the variation and correlation are indeed very significant. In order to make systematic analysis feasible, we apply Stochastic Timed Marked Graph (STMG) as a formal model to capture essential timing related behaviors of parallel multimedia processing systems. Then, we show how the local timing variations and correlations interact and propagate to the global timing behavior; from this we conclude general parallelization guidelines. Furthermore, we develop an analytical performance estimation technique to derive the probability distribution of timing behavior for parallel multimedia processing systems that have correlated stochastic timing behaviors inside. The estimation technique is based on principal component analysis and approximations.

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Data Transfer and Storage Architecture Issues and Exploration in Multimedia Processors

Cited by 9 publications

References 0 publications

Memory aware HLS and the implementation of ageing vectors

Memory aware HLS and the implementation of ageing vectors

Memory accesses management during high level synthesis

Statistical Performance Analysis and Estimation for Parallel Multimedia Processing

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